Hsc Clocks - Vocality V100 Technical Manual

C H A P T E R 4 F E A T U R E S
then communicate as if over a standard aggregate port, but since data packets are being transferred over
the private HSC bus, they incur no extra multiplexing overhead than normal.
Since bandwidth on the HSC is used for both control and data packets, the maximum aggregate of all
data routes via the HSC must not exceed 2Mbps in either direction, so as to allow control packets to flow
under all circumstances.
The HSC uses an RS485-style electrical interface and consists of RX and TX data pairs and separate RX
and TX clocks. All signals are bussed between units by a twisted-pair cable and consist of one driving
source and one receiver. In the example below, the master unit has an aggregate link to a remote unit
and is linked via the HSC to the slave. Data for a tributary port on the slave is received by the master,
routed to the slave and output from the relevant tributary channel.
4.9.2

HSC Clocks

The example above shows the simplest clock application, where the aggregate RX clock drives the GRX of
the master and is also looped back to the TX clock. The GRX is then used as the reference to derive the
4Mbps HSC RX clock. The HSC clock on the slave must be set to drive the GRX clock. This GRX then
becomes the reference for the tributary PLLs in the slave, which derive the port clocks.
Each HSC clock bus must have only one driving source. However, either unit may be designated as the
source for the clock (configure a non-HSC source for GRX/GTX), irrespective of whether it is the master or
V100 Versatile Multiplexer Technical Manual Version 2.2
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