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4.7.2
Global Clocks
There are two Global Clock busses internal to the V100 chassis, the purpose of which is to make a
common clock signal available to all resources in the system. The busses may be driven by the RX or TX
clock from any port or may be used as a reference by the PLLs of any port in the system. Generally, one
of them is associated with the input data clock of the aggregate nominated as the master clock source.
This one is used as the reference source for tributary data ports, voice channels and the 4Mbps High-
speed Serial Channel.
Using this technique, it is possible to onward-link a clock from any port to any other in a V100 network,
even if it is located in another chassis or even in a remote location via a satellite link.
It is essential that only one clock is configured to drive the GRX clock bus (">GRX") and one clock is
configured to drive the GTX clock bus (">GTX") otherwise contention will result – this requirement is met
by the CLOCKING menu. Any number of PLLs may use the GRX or GTX busses as their reference ("<GRX"
or <GTX")
4.7.3
Phase-Locked Loops
The HSC and all data ports each have two independent Phase-locked Loops (PLLs) for the derivation of
RXC or TXC. The reference clock for the PLLs is derived from the internal system clock or from either the
V100 Versatile Multiplexer Technical Manual Version 2.2
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C H A P T E R
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F E A T U R E S
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