Memory System - Sun Microsystems Sun Ultra 60 Service Manual

4
Glueless four-processor connection with minimum latency
4 Snooping cache coherency
4 Four-way superscalar design with nine execution units; four integer execution
units
4 Three floating-point execution units
4 Two graphics execution units
4 Selectable little- or big-endian byte ordering
4 64-bit address pointers
4 16-Kbyte non-blocking data cache
4 16-Kbyte instruction cache; single cycle branch following
4 Power management
4 Software prefetch instruction support
4 Multiple outstanding requests
C.1.4

Memory System

The memory system (Figure C–3) consists of three components: the QSC ASIC, the
XB9+ ASIC, and the memory module. The QSC ASIC generates memory addresses
and control signals to the memory module. The QSC ASIC also coordinates the data
transfers among the DIMMs through two 144-bit-wide processor data buses
(UPA_DATA0 and UPA_DATA1) and the two I/O data bus; UPA_DATA2 and
UPA_DATA3.
DIMMs are organized in banks in groups of four (quads). DIMM capacities of
16-Mbyte, 32-Mbyte, 64-Mbyte, and 128-Mbyte are supported by the memory
module. When all DIMM banks are populated with 128-Mbyte DIMMs, maximum
memory capacity is 2 gigabytes.
Organizing the four DIMM banks with 128-Mbyte (plus ECC bit) DIMMs allows data
streams to be transferred on a 512-bit-wide (plus ECC) memory data bus.
UPA_DATA0, UPA_DATA1, UPA_DATA2, and UPA_DATA3 bus switching The XB9+
ASIC is controlled by the QSC ASIC and performs all data bus switching.
C-7
Functional Description