Sun Microsystems Sun Ultra 60 Service Manual page 229

MBps
Mbps
MHz
MII
ns
NVRAM
OBP
PCI
PCIO
PCMCIA
PID
POR
POST
RAMDAC
RC
RISC
Megabyte per second.
Megabit per second.
Megahertz.
Media independent interface.
Nanosecond.
Non-volatile random-access memory. Stores system variables used
by the boot PROM. Contains the system hostID number and
Ethernet address.
OpenBoot PROM. A routine that tests the network controller,
diskette drive system, memory, cache, system clock, network
monitoring, and control registers.
Peripheral component interconnect. A high-performance 32- or
64-bit-wide bus with multiplexed address and data lines.
PCI-to-EBus/Ethernet controller. An ASIC that bridges the PCI bus
to the EBus, enabling communication between the PCI bus and all
miscellaneous I/O functions, as well as the connection to slower
on-board functions.
Personal computer memory card international association.
Process ID.
Power-on reset.
Power-on self-test. A series of tests that verify system board
components are operating properly. Initialized at system power-on
or when the system is rebooted.
RAM digital-to-analog converter. An ASIC responsible for direct
interface to 3DRAM. Also provides on-board phase-lock loop (PLL)
and clock generator circuitry for the pixel clock.
Resistive-capacitive.
Reset, interrupt, scan, and clock. An ASIC responsible for reset,
interrupt, scan, and clock.
Glossary-3