Sun Microsystems Sun Ultra 60 Service Manual page 181

C
APPENDIX
Functional Description
This section provides a functional description for the Ultra 60 computer (system unit).
4 Section C.1 "System Unit" on page 11-1
4 Section C.2 "Power Supply" on page 11-33
4 Section C.3 "Motherboard" on page 11-39
4 Section C.4 "Jumper Descriptions" on page 11-41
4 Section C.5 "Enclosure" on page 11-43
4 Section C.6 "Environmental Compliance" on page 11-44
4 Section C.7 "Agency Compliance" on page 11-45
C.1 System Unit
The system unit is an UltraSPARC port architecture (UPA)-based multiprocessor
machine that uses peripheral component interconnect (PCI) as the I/O bus. The CPU
modules, U2P ASIC (UPA-to-PCI bridge), and UPA graphics cards communicate with
each other using the UPA protocol. The CPU modules and the U2P ASIC are UPA
master-slave devices. The UPA graphics cards are UPA slave-only devices. The QSC
ASIC routes UPA requests packets through the UPA address bus and controls the
flow of data using the XB9+ ASIC. See Figure C–1.
4 Section C.1.1 "UPA" on page C-4
4 Section C.1.2 "PCI Bus" on page C-5
4 Section C.1.3 "UltraSPARC II Processor" on page C-6
4 Section C.1.4 "Memory System" on page C-7
4 Section C.1.5 "Graphics and Imaging" on page C-12
C-1