Sun Microsystems Sun Ultra 60 Service Manual page 211

C.1.13.2 QSC
The QSC ASIC provides system control. It controls the UPA interconnect between the
major system unit components and main memory. The QSC ASIC provides the
following:
4 Interconnect packet receive
4 Memory arbiter
4 Non-cached arbiter
4 Memory controller
4 Snoop interface
4 Coherence controller
4 S_register dispatcher
4 Internet packet send
4 Datapatch scheduler
4 EBus interface
C.1.13.3 PCIO
The PCI-to-EBus/Ethernet controller (PCIO) ASIC performs dual roles: PCI
bus-to-Ebus bridging and Ethernet control. The PCIO ASIC provides the electrical
connection between the PCI bus and all other I/O functions. In addition, the PCIO
ASIC also contains an embedded Ethernet controller to manage Ethernet transactions
and provides the electrical connection to slower on-board functions, such as the
Flash PROM and the audio module.
C.1.13.4 U2P
The UPA-to-PCI bridge (U2P) ASIC provides an I/O connection between the UPA
bus and the two PCI buses. The U2P ASIC features include:
4 Full master and slave port connection to the high-speed UPA interconnect. The
UPA is a split address/data packet-switched bus that has a potential data
throughput rate of greater than 1 Gbyte per second. UPA data is ECC protected.
4 Two physically separate PCI bus segments with full master and slave support:
4
66-MHz PCI bus segment (PCI bus A): 3.3-Vdc I/O signaling, 64-bit data bus,
compatible with the PCI 66-MHz extensions, support for up to four master
devices (at 33 MHz only)
4
33-MHz PCI bus segment (PCI bus B): 5.0-Vdc I/O signaling, 64-bit data bus,
support for up to six master devices
C-31
Functional Description