Table 3-11. Lvds Video Interface Pin Signals (J23) - ADLINK Technology CoreModule 720 Reference Manual

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Chapter 3
Table 3-10. SDVO Interface Pin Signals (J15) (Continued)
Pin #
Signal
20
SDVO_I2C_CLK
21
SDVO_I2C_DAT
22
RESET
23
+3.3V_1
24
+2.5V
25
+5V_1
26
GND8
27
SDVO_TVCLKIN-
28
SDVO_TVCLKIN+
29
+3.3V_2
30
+5V_2
Note: The shaded table cells denote power or ground.
Table 3-10
lists the pin signals of the LVDS video header, which provides 20 pins, 2 rows, odd/even pin
sequence (1, 2) with 0.079" (2mm) pitch.

Table 3-11. LVDS Video Interface Pin Signals (J23)

Pin #
Signal
1
+12V
2
VCC_LVDS_CONN
3
GND
4
GND
5
LVDSA_CLK_P
6
LVDSA_CLK_N
7
LVDSA_DAT3_P
8
LVDSA_DAT3_N
9
LVDSA_DAT2_P
10
LVDSA_DAT2_N
11
LVDSA_DAT1_P
12
LVDSA_DAT1_N
13
LVDSA_DAT0_P
14
LVDSA_DAT0_N
15
LBKLT_CTL
16
LVDD_EN
17
LDDC_CLK
18
LDDC_DATA
19
LBKLT_EN
20
NC
Note: The shaded table cells denote power or ground.
28
Description
I2C control signal (Clock) for SDVO device
I2C control signal (Data) for SDVO device
Reset signal
+3.3 Volt Power 1
+2.5 Volt Power
+5 Volt Power 1
Ground 8
SDVO TV-Out Synchronization Clock Input - Negative
SDVO TV-Out Synchronization Clock Input - Positive
+3.3 Volt Power 2
+5 Volt Power 2
Description
+12 volts for flat panel and backlight
JP3 determines LVDS voltage (+3.3V or +5V)
Ground
Ground
LVDS A Clock Positive
LVDS A Clock Negative
LVDS A DATA Positive Line 3
LVDS A DATA Negative Line 3
LVDS A DATA Positive Line 2
LVDS A DATA Negative Line 2
LVDS A DATA Positive Line 1
LVDS A DATA Negative Line 1
LVDS A DATA Positive Line 0
LVDS A DATA Negative Line 0
Panel Backlight Control
Enable Panel Power
Display Data Channel Clock
Display Data Channel Data
Enable Backlight Inverter
Not Connected
Reference Manual
Hardware
CoreModule 720

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