Printronix T3204 Maintenance Manual page 96

The ADDRRST signal is sent the FPGA (U50) from the PIC. This signal is
used to reset the FPGA RAM address counter prior to the beginning of the
next "LOAD RAM" load cycle.
The LOADRAM signal is sent to the FPGA from the PIC. This signal is used
to tell the FPGA when a new "LOAD RAM" cycle is about to begin.
The GBINT signal is sent from the FPGA to the PIC. This signal is generated
when the FPGA detects the 9th bit of the FIFO data is high which indicates
that the last byte of the column has been stored in the FIFO.
The BURNIRQ signal goes from the FPGA to the PIC. This signal is a
decode of the RAM address lines. This signal is used to inform the PIC when
a burn cycle has been completed.
Each dot row that is printed is made up of 6 heat cycles. The CYCNT signal
coming from the PIC and going to the FPGA is used to clock the 3-bit heat
cycle counter (located inside the FPGA) from one heat cycle to the next.
The LATCH signal is generated by the PIC. This signal is used to latch serial
printhead data into the printhead output latches. The –STB signal is
generated by the PIC. This signal is used to enable the printhead drivers.
Any driver that has a "ONE" written to its corresponding latch flip-flop will
activate its thermal element. Any driver with a "ZERO" written to its
corresponding latch flip-flop will de-activate its thermal element.
RS232 Drivers and Receivers
The RS232 drivers and receivers are all contained in one chip (U44). This
chip has two RS232 drivers and two RS232 receivers. This chip also
contains charge pump circuitry used to convert +5 volts to +10 volts and –10
volts (these voltages are required by the RS232 drivers).
The received data present on U44–12 is AND'ed with the RS422 output by
U25. When either the RS232 or RS422 receivers are not receiving serial
input data their respective outputs will be in the HIGH state
(U44–12 and U39–3).
8–12 Circuit Description