Printronix T3204 Maintenance Manual page 90

Programmable Logic Device
The Programmable Logic Device (U54) performs a multitude of functions
related to memory and I/O control. The majority of these functions are listed
below:
1. Provides refresh to the DRAM chips by generating a CAS before RAS
once every 15 microseconds (approximately).
2. Serves as a wait state generator that can generate wait states and
stretched control signals for each bus read/write cycle. The wait states
generated are listed below.
DRAM, PIC16C55, FIFO and Operator Panel status
Memory cartridge connector (J19) and NVRAM (option)
A–D converter (U29), clock/calendar (U38) and Op Panel display
All other read/write cycle
3. Generates the DRAM control signals (–COL, –WE0, –WE, –RAS0,
–RAS1, –RAS2, –CAS0L,
–CAS0H, –CAS1L, –CAS1H, –CAS2, –CAS3, –CAS4, –CAS5).
4. Generates the memory and I/O chip select signals (–EPSEL,
CARTDEN, –IOWR, –RCMD, NIDSEL, NMSEL, NDSEL, –RDFIFO,
–RDSEN, –RDFPAN, –DISPDEN, –NVRCE, –RTCSEL).
5. Generates one of the 80960 bus control signals (–RDY).
6. Provides a 25 MHz clock for the processor, a 16 MHz clock for print
control FPGA (U50) and the PIC16C55 (U48) microcontroller, an 8 MHz
clock for the UART (U45) and an 8 Msec clock for the 80960JA.
Memory Cartridge Interface
The interface to the memory cartridges is comprised of connector J19, and
data transceivers U3 and U5, address lines and control buffers U4 and U28.
The printer software has been written to automatically detect the presence of
a plug-in cartridge.
NOTE: The cartridge can be plugged-in with AC power ON or OFF.
ST16C1451CJ UART
U45 is a device that converts serial data to parallel data or converts parallel
data to serial data. It is called a Universal Asynchronous Receiver
Transmitter (UART). It can convert serial data at speeds as fast as 19,200
bits per second.
8–6
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . One wait state
. . . . . . . . . . . . . Three wait states
. . . . . Seven wait states
Two wait states
Circuit Description