Logical Schematic Of Smbus Circuitry - Intel Itanium 2 Processor Datasheet
2 processor 1.66 ghz with 9 mb l3 cache / 1.66 ghz with 6 mb l3 cache / 1.6 ghz with 9 mb l3 cache / 1.6 ghz with 6 mb l3 cache/ 1.5 ghz with 6 mb l3 cache / 1.5 ghz with 4 mb l3 cache / 1.4 ghz with 4 mb l3 cache / 1.3 ghz with 3 mb l3 cache / 1.0 ghz wi
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System Management Feature Specifications
Figure 6-1. Logical Schematic of SMBus Circuitry
10K
10K
SMA0
SMA1
3.3V
SMA2
System Board
NOTE:
1. Actual implementation may vary.
2. For use in general understanding of the architecture.
80
3.3V
10K
V
CC
A0
A1
SC
Processor
Information
A2
SD
ROM
V
CC
A0
SC
A1
SD
Scratch
EEPROM
A2
WP
SMWP
3.3V
Stuffing
Options
10K
10K
VCC
A0
Thermal
Sensing
A1
10K
ALERT
SMSD
SMSC
THRMALERT#
System Board
Intel
®
Itanium
®
2 Processor
Core
THERMDA
THERMDC
STBY
SC
SD
Device
3.3V
10K
Datasheet
000668b
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