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Figure 7-2.
Logical Schematic of SMBus Circuitry
Note:
Actual implementation may vary. This figure is provided to offer a general understanding of the
architecture. All SMBus pull-up and pull-down resistors are 10 kΩ and located on the processor.
7.4.1
SMBus Device Addressing
Of the addresses broadcast across the SMBus, the memory component claims those of
the form "1010XXXZb". The "XXX" bits are defined by pull-up and pull-down resistors
on the system baseboard. These address pins are pulled down weakly (10 kΩ) on the
processor substrate to ensure that the memory components are in a known state in
systems which do not support the SMBus (or only support a partial implementation).
The "Z" bit is the read/write bit for the serial bus transaction.
Note that addresses of the form "0000XXXXb" are Reserved and should not be
generated by an SMBus master. The system designer must also ensure that their
particular implementation does not add excessive capacitance to the address inputs.
Excess capacitance at the address inputs may cause address recognition problems.
Refer to the appropriate platform design guide document.
Figure 7-2
address pin connections and how they affect the addressing of the devices.
Document Number: 318080-002
SM_VCC
SM_EP_A0
SM_EP_A1
SM_EP_A2
SM_WP
SM_CLK
SM_DAT
shows a logical diagram of the pin connections.
VCC
DATA
Processor
CLK
Information
ROM
and Scratch
EEPROM
(1Kbit each)
VSS
Table 7-3
describe the
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