Bist Flow Chart; Bist Implementation - Intel NetStructure MPCMM0001 Software Instructions

Built-In Self Test (BIST)
Figure 1.

BIST Flow Chart

Power Up/
Reset
BlueCat
loaded (active
CMM)
IPMB
Bus Test
BlueCat
Image
Checksum
The BIST has been broken down into stages consisting of groups of tests that run at certain times
throughout the boot process. The following table shows the different BIST stages and the tests
associated with each stage:
Table 4.

BIST Implementation

Boot-BIST
RedBoot image
checksum
FPGA image checksum
Base memory test
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RB image pass
RB image
Run from
and backup
backup
RB image
RB
checksum
FPGA,
DS1307, NIC
Early-BIST
Strobe WDT to extend
timeout period
Jump to
run from
RB
FPGA image
RB image fail
and backup
FPGA image
checksum
backup FPGA
image pass
and FPGA
image fail
Load backup Load FPGA
FPGA image image
Memory Test
Mid-BIST
Extended memory test
FPGA version check
DS1307 RTC test
Local PCI bus/NIC
presence test
NOT (backup
FPGA image
pass and
FPGA image
fail)
Late-BIST
BlueCat image checksum
IPMB bus test