Digital Video Input Connectors - Matrox Helios Series Installation And Hardware Reference

140 Appendix B: Technical information
Pin Signal
1 P0_LVDS_DATA_IN0+
2 P0_LVDS_DATA_IN0-
3 P0_LVDS_DATA_IN1+
4 P0_LVDS_DATA_IN1-
5 P0_LVDS_DATA_IN2+
6 P0_LVDS_DATA_IN2-
7 P0_LVDS_DATA_IN3+
8 P0_LVDS_DATA_IN3-
9 P0_LVDS_DATA_IN4+
10 P0_LVDS_DATA_IN4-
11 P0_LVDS_DATA_IN5+
12 P0_LVDS_DATA_IN5-
13 P0_LVDS_DATA_IN6+
14 P0_LVDS_DATA_IN6-
15 P0_LVDS_DATA_IN7+
16 P0_LVDS_DATA_IN7-
17 P0_LVDS_DATA_IN8+
18 P0_LVDS_DATA_IN8-
19 P0_LVDS_DATA_IN9+

Digital video input connectors

The two digital connectors are 100-pin low-profile IDC female connectors
(receptacles). They are used to receive video input signals and transmit/receive
timing, synchronization, and communication signals between the video source
and the frame grabber.
Connector 0 has the following pinout:
Description
Data bit 0 for acq. path 0, in LVDS format (positive).
Data bit 0 for acq. path 0, in LVDS format (negative).
Data bit 1 for acq. path 0, in LVDS format (positive).
Data bit 1 for acq. path 0, in LVDS format (negative).
Data bit 2 for acq. path 0, in LVDS format (positive).
Data bit 2 for acq. path 0, in LVDS format (negative).
Data bit 3 for acq. path 0, in LVDS format (positive).
Data bit 3 for acq. path 0, in LVDS format (negative).
Data bit 4 for acq. path 0, in LVDS format (positive).
Data bit 4 for acq. path 0, in LVDS format (negative).
Data bit 5 for acq. path 0, in LVDS format (positive).
Data bit 5 for acq. path 0, in LVDS format (negative).
Data bit 6 for acq. path 0, in LVDS format (positive).
Data bit 6 for acq. path 0, in LVDS format (negative).
Data bit 7 for acq. path 0, in LVDS format (positive).
Data bit 7 for acq. path 0, in LVDS format (negative).
Data bit 8 for acq. path 0, in LVDS format (positive).
Data bit 8 for acq. path 0, in LVDS format (negative).
Data bit 9 for acq. path 0, in LVDS format (positive).
51
1
100
50