Matrox Helios Series Installation And Hardware Reference page 129

Pin Signal
6 P1_TTL_AUX(EXP)_OUT
7 P1_RS232_RxD
8 P1_RS232_TxD
9 P1_LVDS/TTL_CHSYNC_IO-
10 P1_LVDS/TTL_CHSYNC_IO+
11 GND
12 P0_LVDS/TTL_CHSYNC_IO-
13 P0_LVDS/TTL_CHSYNC_IO+
14 P0_TTL_AUX(TRIG)_IN
15 GND
16 P0_RS232_TxD
Pin Signal
1 P3_LVDS/TTL_VSYNC_IO-
2 P3_LVDS/TTL_VSYNC_IO+
3 GND
Description
TTL auxiliary output for acq. path 1.
Supported signals: exposure output 0
(main purpose) or user output 2.
RS-232 serial port 1 to frame grabber
(UART).
RS-232 serial port 1 to video source
(UART).
CSYNC input or HSYNC input/output for
acq. path 1 (negative).
CSYNC input or HSYNC input/output for
acq. path 1 (positive).
Ground.
CSYNC input or HSYNC input/output for
acq. path 0 (negative).
CSYNC input or HSYNC input/output for
acq. path 0 (positive).
TTL auxiliary input for acq. path 0.
Supported signals: trigger input 0
(main purpose), field input, or user
input 0.
Ground.
RS-232 serial port 0 to video source
(UART).
The pinout for DVI connector 1 is as follows:
Description
VSYNC input/output for acq. path 3
(negative).
VSYNC input/output for acq. path 3
(positive).
Ground.
Connectors on Matrox Helios eA/XA
Pin Signal
22 P1_TTL_AUX(TRIG)_IN
23 P0_TTL_AUX(EXP)_OUT
24 P0_RS232_RxD
C1 P0_VID_IN_A
C2 P1_VID_IN_A
C3 P2_VID_IN_A
C4 P3_VID_IN_A
C5 GND
C6 GND
M1 GND
M2 GND
Pin Signal
17 P3_LVDS/TTL_CLK_IO-
18 P3_LVDS/TTL_CLK_IO+
19 GND
129
Description
TTL auxiliary input for
acq. path 1.
Supported signals:
trigger input 0 (main
purpose), field input, or
user input 0.
TTL auxiliary output for
acq. path 0.
Supported signals:
exposure output 0
(main purpose) or user
output 2.
RS-232 serial port 0 to
frame grabber (UART).
Video input A for acq.
path 0 (AC/DC).
Video input A for acq.
path 1 (AC/DC).
Video input A for acq.
path 2 (AC/DC).
Video input A for acq.
path 3 (AC/DC).
Ground.
Ground.
Ground.
Ground.
Description
Clock input/output for
acq. path 3 (negative).
Clock input/output for
acq. path 3 (positive).
Ground.