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12 Chapter 1: Introduction
Second
& Syncs (4)
MDR-26
connector
& Syncs (4)
& Syncs (4)
First
Cam Ctrl (4)
MDR-26
connector
HSYNC Out (1)
VSYNC Out (1)
Clock Out (1)
DB-44 and
DB-9
Aux Out (2)
3
connectors
Aux I/Os (4)
OptoAux (4)
System
From reset button
reset
To motherboard
connector
1. 20 bits serialized across 4 LVDS pairs.
2.
28 bits serialized across 4 LVDS pairs.
3.
On a separate bracket.
4. Refer to the "Synchronization and control signals" section for details.
Matrox Helios eCL/XCL single-Full
Clock
ChannelLink
Data (16)
Receiver #3
1
Clock
ChannelLink
Data (24)
Receiver #2
2
Data (24)
2
ChannelLink
Receiver #1
Clock
LVDS
drivers
SerTFG
LVDS driver
SerTC
& receiver
UART
LVDS
drivers
and
4
Aux In (4)
receivers
4
4
TTL buffers
Opto-coupler
16
Video
64
24
to
LUTs
PCI-X
Bridge
24
Flash
EEPROM
PSG
Watchdog
Host PCIe/PCI/PCI-X bus
On-board
main memory
(128 MB/256 MB)
512 MB/1 Gb
128 DDR
(up to 5.3 GB/s)
64
Link 1
Matrox
Oasis
Link 0
64
(up to 1 GB/s)
PCI-X to PCIe (eCL)
or PCI-X to PCI-X (XCL)
Bridge
64
(up to 1 GB/s)
5V/3.3V
x4 PCIe (eCL)
PCI/PCI-X
(XCL)
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