Uarts; Psgs - Matrox Helios Series Installation And Hardware Reference

76 Chapter 4: Matrox Helios hardware reference
Lookup tables
The board has programmable lookup tables (LUTs). The LUTs can be operated
in the following configurations:
• 8 palettes of one, two, three, four, or eight 256-entry 8-bit LUTs.
• 4 palettes of one, two, three, or four 1024-entry 8- or 16-bit LUTs.
• 1 palette of one, two, three, or four 4096-entry 8- or 16-bit LUTs.
14- and 16-bit data by-pass the LUTs.
The LUTs are programmed using the MIL-Lite function MdigLut().

UARTs

For each acquisition path, the module supports an RS-232 compatible serial
interface. Each interface is mapped as a COM port so that it can be accessed
through the Win32 API. Each interface is comprised of both a transmit port and
a receive port, permitting the interface to work in full-duplex mode. The interfaces
are on External auxiliary I/O connector 0.
Each interface is controlled by a Universal Asynchronous Receiver-Transmitter
(UART). The UART features independently programmable baud rates,
supporting all standard baud rates from 300 baud up to 115200
addition, the UART has an internal 8-byte FIFO memory buffer, and can generate
system level interrupts for both transmit and receive operations.

PSGs

Each acquisition path has its own programmable synchronization generator
(PSG). The PSGs allow Matrox Helios eD/XD to adapt to many video standards.
The PSGs are responsible for managing all video timing, synchronization, trigger,
exposure, and user-defined input and output signals.
Each PSG allows for independent acquisition from video sources. Therefore,
Matrox Helios eD/XD allows acquisition from four independent video sources.
1. For example, two 256-entry 8-bit LUTs can map 2-tap, 8-bit data to 8-bit values. In
addition, one 1024-entry 8-bit LUT can map 1-tap, 10-bit data to 8-bit values.
2. Note that the maximum baud rate is highly dependant on the amount of computer
resources available.
1
2
baud. In