Matrox Helios Series Installation And Hardware Reference page 146

146 Appendix B: Technical information
Pin Signal
50 GND
51 P3_LVDS_DATA_IN0+
52 P3_LVDS_DATA_IN0-
53 P3_LVDS_DATA_IN1+
54 P3_LVDS_DATA_IN1-
55 P3_LVDS_DATA_IN2+
56 P3_LVDS_DATA_IN2-
57 P3_LVDS_DATA_IN3+
58 P3_LVDS_DATA_IN3-
59 P3_LVDS_DATA_IN4+
60 P3_LVDS_DATA_IN4-
61 P3_LVDS_DATA_IN5+
62 P3_LVDS_DATA_IN5-
63 P3_LVDS_DATA_IN6+
64 P3_LVDS_DATA_IN6-
65 P3_LVDS_DATA_IN7+
66 P3_LVDS_DATA_IN7-
67 P3_LVDS_DATA_IN8+
68 P3_LVDS_DATA_IN8-
69 P3_LVDS_DATA_IN9+
70 P3_LVDS_DATA_IN9-
71 P3_LVDS_DATA_IN10+
72 P3_LVDS_DATA_IN10-
73 P3_LVDS_DATA_IN11+
74 P3_LVDS_DATA_IN11-
75 P3_LVDS_DATA_IN12+
76 P3_LVDS_DATA_IN12-
77 P3_LVDS_DATA_IN13+
78 P3_LVDS_DATA_IN13-
79 P3_LVDS_DATA_IN14+
80 P3_LVDS_DATA_IN14-
81 P3_LVDS_DATA_IN15+
82 P3_LVDS_DATA_IN15-
83 P3_LVDS_HSYNC_IN+
Description
Ground
Data bit 0 for acq. path 3, in LVDS format (positive).
Data bit 0 for acq. path 3, in LVDS format (negative).
Data bit 1 for acq. path 3, in LVDS format (positive).
Data bit 1 for acq. path 3, in LVDS format (negative).
Data bit 2 for acq. path 3, in LVDS format (positive).
Data bit 2 for acq. path 3, in LVDS format (negative).
Data bit 3 for acq. path 3, in LVDS format (positive).
Data bit 3 for acq. path 3, in LVDS format (negative).
Data bit 4 for acq. path 3, in LVDS format (positive).
Data bit 4 for acq. path 3, in LVDS format (negative).
Data bit 5 for acq. path 3, in LVDS format (positive).
Data bit 5 for acq. path 3, in LVDS format (negative).
Data bit 6 for acq. path 3, in LVDS format (positive).
Data bit 6 for acq. path 3, in LVDS format (negative).
Data bit 7 for acq. path 3, in LVDS format (positive).
Data bit 7 for acq. path 3, in LVDS format (negative).
Data bit 8 for acq. path 3, in LVDS format (positive).
Data bit 8 for acq. path 3, in LVDS format (negative).
Data bit 9 for acq. path 3, in LVDS format (positive).
Data bit 9 for acq. path 3, in LVDS format (negative).
Data bit 10 for acq. path 3, in LVDS format (positive).
Data bit 10 for acq. path 3, in LVDS format (negative).
Data bit 11 for acq. path 3, in LVDS format (positive).
Data bit 11 for acq. path 3, in LVDS format (negative).
Data bit 12 for acq. path 3, in LVDS format (positive).
Data bit 12 for acq. path 3, in LVDS format (negative).
Data bit 13 for acq. path 3, in LVDS format (positive).
Data bit 13 for acq. path 3, in LVDS format (negative).
Data bit 14 for acq. path 3, in LVDS format (positive).
Data bit 14 for acq. path 3, in LVDS format (negative).
Data bit 15 for acq. path 3, in LVDS format (positive).
Data bit 15 for acq. path 3, in LVDS format (negative).
HSYNC input for acq. path 3, in LVDS format (positive).