Matrox Helios Series Installation And Hardware Reference page 66

66 Chapter 4: Matrox Helios hardware reference
PSGs
Matrox Helios eA/XA features four programmable synchronization generators
(PSGs). The PSGs are responsible for managing all video timing, synchronization,
trigger, exposure, and user-defined input and output signals. The PSGs on Matrox
Helios eA/XA allow the board to adapt to many video standards. Each PSG allows
for independent acquisition from a video source. Therefore, Matrox Helios eA/XA
allows acquisition from four independent video sources.
The phase-locked loop
The high-performance, low-jitter phase-locked loop (PLL) uses frequency
synthesis techniques to generate the clock signal in slave mode.
As a reference, the PLL uses the composite or horizontal video synchronization
signal supplied by the video source (line-locked mode).
Since the signal from the video source is used as a reference, the PLL can produce
a clock signal that is a multiple of it. In addition, using a programmable delay line,
you can phase-shift the clock signal; this allows you to fine-tune the location at
which the video signal is sampled so that you can compensate for errors when
digitizing close to or at the Nyquist frequency.
Operating frequency range
Jitter
Phase adjustment
When the input source supplies a sampling clock that does not require adjustment,
the PLL is bypassed to avoid adding jitter to the supplied clock.
Synchronization and control signals
The following tables summarize the synchronization, timing, and control signals
supported by Matrox Helios eA/XA. Most of these signals are available by defining
auxiliary (general purpose) signals as such in the DCF. When an acquisition path
supports several signals of a specific type, the tables identify the one to which an
Specification
12 to 80 MHz
4.6 nsec p-p absolute with RS-170 synchronization source
256 steps of 0.5 nsec