Matrox Helios Series Installation And Hardware Reference page 121

Pin Signal
11 P0_LVDS_CLK_OUT+
12 LVDS_AUX_IN1+
13 P0_TTL_AUX_IO_1
14 GND
15 TTL_AUX_IO_1
16 GND
17 P1_LVDS_AUX_OUT1-
18 P1_LVDS_AUX_OUT0-
19 P0_LVDS_AUX_OUT1+
20 P0_LVDS_AUX_OUT0+
21 P1_LVDS_VSYNC_OUT-
22 P1_LVDS_CLK_OUT-
23 P0_LVDS_AUX_IN1-
24 OPTO_AUX_IN0+
25 P0_LVDS_VSYNC_OUT-
26 P0_LVDS_HSYNC_OUT-
Description
Clock output for acq. path 0 (positive).
LVDS auxiliary input 1 for an unspecified acq. path (positive).
Signals only supported for acq. path 0: user input 11.
Signals only supported for acq. path 1: trigger input 1, user input 6, timer clock input, or quadrature input
bit 1.
Signals supported for any acq. path: trigger input 3.
TTL auxiliary input/output 1 for acq. path 0.
Supported signals: exposure output 0, trigger input 1, user input/output 3.
Ground.
TTL auxiliary input/output 1 for an unspecified acq. path.
Signals only supported for acq. path 0: user input/output 7.
Signals only supported for acq. path 1: exposure output 1, user input/output 4.
Signals supported for any acq. path: trigger input 3.
Ground.
LVDS auxiliary output 1 for acq. path 1 (negative).
See pin 2 for more information.
LVDS auxiliary output 0 for acq. path 1 (negative).
See pin 33 for more information.
LVDS auxiliary output 1 for acq. path 0 (positive).
Supported signals: exposure output 1, user output 6.
LVDS auxiliary output 0 for acq. path 0 (positive).
Supported signals: exposure output 0, user output 5.
VSYNC output for acq. path 1 (negative).
See pin 36 for more information.
Clock output for acq. path 1 (negative).
See pin 7 for more information.
LVDS auxiliary input 1 for acq. path 0 (negative).
See pin 37 for more information.
Opto-isolated auxiliary input 0 for an unspecified acq. path (positive).
Signals only supported for acq. path 0: user input 8.
Signals only supported for acq. path 1: trigger input 0, user input 0, field polarity input.
Signals supported for any acq. path: trigger input 2.
VSYNC output for acq. path 0 (negative).
See pin 40 for more information.
HSYNC output for acq. path 0 (negative).
See pin 41 for more information.
Connectors on Matrox Helios eCL/XCL 121