Matrox Helios Series Installation And Hardware Reference page 11

SerTFG
SerTC
Second
MDR-26
Cam Ctrl (4)
connector
Data (24)
& Syncs (4)
Data (24)
& Syncs (4)
First
Cam Ctrl (4)
MDR-26
connector
SerTFG
HSYNC Out (2)
VSYNC Out (2)
DB-44 and
Clock Out (2)
DB-9
Aux In(4)
2
connectors
Aux Out(4)
Aux I/O(6)
OptoAux(4)
System
From reset button
reset
To motherboard
connector
1.
28 bits serialized across 4 LVDS pairs.
2.
On a separate bracket.
3. Refer to the "Synchronization and control signals" section for details.
UART
LVDS driver
& receiver
LVDS
drivers
Clock
ChannelLink
24
Receiver #2
1
24
1
ChannelLink
Receiver #1
Clock
LVDS
drivers
LVDS driver
& receiver
SerTC
UART
LVDS
drivers
and
3
receivers
3
3
TTL buffers
Opto-coupler
Matrox Helios eCL/XCL dual-Base
PSG #1
32
LUTs
Video
PCI-X
Bridge
32
LUTs
Flash
EEPROM
PSG #0
Watchdog
Host PCIe/PCI/PCI-X bus
Matrox Helios boards
On-board
main memory
(128/256 MB
512 MB/1 GB)
128 DDR
(up to 5.3 GB/s)
64
to
Link 1
Matrox
Oasis
Link 0
64
(up to 1 GB/s)
PCI-X to PCIe (eCL)
or PCI-X to PCI-X (XCL)
Bridge
64
(up to 1 GB/s)
5V/3.3V
x4 PCIe (eCL)
PCI/PCI-X
(XCL)
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