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Pin
Signal
20
P0_LVDS_DATA_IN9-
21
P0_LVDS_DATA_IN10+
22
P0_LVDS_DATA_IN10-
23
P0_LVDS_DATA_IN11+
24
P0_LVDS_DATA_IN11-
25
P0_LVDS_DATA_IN12+
26
P0_LVDS_DATA_IN12-
27
P0_LVDS_DATA_IN13+
28
P0_LVDS_DATA_IN13-
29
P0_LVDS_DATA_IN14+
30
P0_LVDS_DATA_IN14-
31
P0_LVDS_DATA_IN15+
32
P0_LVDS_DATA_IN15-
33
P0_LVDS_HSYNC_IN+
34
P0_LVDS_HSYNC_IN-
35
P0_LVDS_AUX(VSYNC)_IN+
36
P0_LVDS_AUX(VSYNC)_IN-
37
P0_LVDS_AUX(CLK)_OUT+
38
P0_LVDS_AUX(CLK)_OUT-
39
P0_LVDS_CLK_IN+
40
P0_LVDS_CLK_IN-
41
P0_LVDS/TTL_AUX(HSYNC)_OUT0+
42
P0_LVDS/TTL_AUX(HSYNC)_OUT0-
43
P0_LVDS/TTL_AUX(VSYNC)_OUT1+
44
P0_LVDS/TTL_AUX(VSYNC)_OUT1-
45
P0_LVDS/TTL_AUX(EXP)_OUT2+
Description
Data bit 9 for acq. path 0, in LVDS format (negative).
Data bit 10 for acq. path 0, in LVDS format (positive).
Data bit 10 for acq. path 0, in LVDS format (negative).
Data bit 11 for acq. path 0, in LVDS format (positive).
Data bit 11 for acq. path 0, in LVDS format (negative).
Data bit 12 for acq. path 0, in LVDS format (positive).
Data bit 12 for acq. path 0, in LVDS format (negative).
Data bit 13 for acq. path 0, in LVDS format (positive).
Data bit 13 for acq. path 0, in LVDS format (negative).
Data bit 14 for acq. path 0, in LVDS format (positive).
Data bit 14 for acq. path 0, in LVDS format (negative).
Data bit 15 for acq. path 0, in LVDS format (positive).
Data bit 15 for acq. path 0, in LVDS format (negative).
HSYNC input for acq. path 0, in LVDS format (positive).
HSYNC input for acq. path 0, in LVDS format (negative).
LVDS auxiliary input for acq. path 0 (positive).
Supported signals: user input 0, trigger input 0, or VSYNC input (main purpose).
LVDS auxiliary input for acq. path 0 (negative).
See pin 35 for more information.
LVDS auxiliary output for acq. path 0 (positive).
Supported signals: user output 0 or clock output (main purpose).
LVDS auxiliary output for acq. path 0 (negative).
See pin 37 for more information.
Clock input for acq. path 0, in LVDS format (positive).
Clock input for acq. path 0, in LVDS format (negative).
LVDS/TTL auxiliary output 0 for acq. path 0 (positive).
Supported signals: HSYNC output (main purpose) or user output 1.
Negative component when LVDS signal arriving on LVDS/TTL auxiliary output 0 for acq. path 0.
See pin 41 for more information.
LVDS/TTL auxiliary output 1 for acq. path 0 (positive).
Supported signals: VSYNC output (main purpose) or user output 2.
Negative component when LVDS signal arriving on LVDS/TTL auxiliary output 1 for acq. path 0.
See pin 43 for more information.
LVDS/TTL auxiliary output 2 for acq. path 0 (positive).
Supported signals: exposure output 0 (main purpose) or user output 3.
Connectors on Matrox Helios eD/XD
141
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