Matrox Helios Series Installation And Hardware Reference page 55

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Type of signal
Frame valid input
VSYNC output
Line valid input
HSYNC output
Data valid input
Clock input
Clock output
1. The maximum # for each signal type cannot always be attained. The actual maximum depends on whether the required auxiliary signals are available or have been
defined as another type.
2. In this column, each signal is a dedicated signal (that is, it cannot be redefined as another type of signal).
3. Clock input is received on the Camera Link connectors, whereas the other signals in this column are received on/transmitted from external auxiliary I/O connector 0
(DB-44).
4. For the single-Full version only.
Camera control
Auxiliary input and
output signals
LVDS cam. ctrl
CL connect. 0
0
1
1
1
0
1
0
0
0
0
1
1
0
1
1
1
0
1
0
0
0
0
1
1
0
1
1
1
0
1
1
1
0
1
0
0
0
0
1
1
As mentioned previously, for each acquisition path, the board supports four
camera control output signals. You can route exposure signals, synchronization
output signals, or user-defined signals to these signals. You specify their purpose
in the DCF file. You can then program them using the MIL-Lite function
MdigControl() with
In addition, the board supports auxiliary multi-purpose input and output signals.
Auxiliary output signals can be routed as exposure signals or user-defined signals
(for controlling external devices, such as a strobe light or programmable logic
controller). Auxiliary input signals can be routed as trigger input (for example, to
Matrox Helios eCL/XCL acquisition section
Received with data
CL connect. 1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
or
M_USER_...
M_GRAB_EXPOSURE...
LVDS dedicated signals
0
P0_LVDS_VSYNC_OUT
P1_LVDS_VSYNC_OUT
0
P0_LVDS_HSYNC_OUT
P1_LVDS_HSYNC_OUT
0
Xclk (CL connect. 0) and
4
4
Yclk
and Zclk
Xclk (CL connect. 1)
P0_LVDS_CLK_OUT
P1_LVDS_CLK_OUT
.
55
2 3
(CL connect. 1)

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