Communication; Uarts; Psgs - Matrox Helios Series Installation And Hardware Reference

Matrox Helios eCL/XCL acquisition section 53
The LUTs are programmed using the MIL-Lite function MdigLut().

Communication

For each acquisition path, two LVDS pairs are used to transmit or receive
asynchronous serial communication between the video source and the board.
These signals are handled by the Universal Asynchronous Receiver/Transmitter(s)

(UARTs).

For each acquisition path, four camera control output signals are also available.
These are general-purpose signals that are sent to the video source.
UARTs
The dual-Base version of Matrox Helios eCL/XCL offers two LVDS compatible
serial interfaces, whereas the single-Full version features only one. Each interface
is mapped as a COM port so that it can be accessed through the Win32 API. Each
interface is comprised of both a transmit port and a receive port, permitting the
interface to work in full-duplex mode.
Each interface is controlled by a Universal Asynchronous Receiver-Transmitter
(UART). Each UART features independently programmable baud rates; each
1
supports all standard baud rates from 300 baud up to 115200 baud. Each has an
internal 8-byte FIFO memory buffer. In addition, each can generate system level
interrupts in both transmit and receive operations.

PSGs

The dual-Base version of Matrox Helios eCL/XCL features two Programmable
Synchronization Generators (PSGs), whereas the single-Full version features only
one PSG. The PSGs are responsible for managing all video timing,
synchronization, triggering, exposure, and user-defined input and output signals.
Each PSG allows for independent acquisition from video sources. Therefore, the
dual-Base version allows acquisition from two independent video sources, whereas
the single-Full version allows acquisition from only one video source.
1. Note that the maximum baud rate is highly dependant on the amount of computer
resources available.