Matrox Helios Series Installation And Hardware Reference page 107

• Acquisition paths can be combined to acquire from:
- Component RGB video source.
- Two dual-tap monochrome video sources.
- Two monochrome video sources at up to 160 Msamples/sec.
• Supports frame and line-scan video sources.
• Four PSGs. For each PSG, there is the following:
- Adjustable clock phase (256 steps with 0.5 ns resolution).
- LVDS/TTL pixel clock, HSYNC, and VSYNC inputs or outputs.
- A TTL auxiliary input (trigger, field polarity, or user input).
- A TTL auxiliary output (exposure or user output).
- An opto-isolated auxiliary input (trigger or user input).
- RS-232 serial port.
- Status LED.
• 128 MB/256 MB/512 MB/1 GB of 167 MHz DDR SDRAM main memory.
Over 5.0 Gbytes/sec of memory bandwidth.
• Eight TTL/LVDS configurable auxiliary inputs (trigger, field polarity, data valid,
timer clock, synchronization, and/or user input). See Matrox Helios hardware
reference for supported configurations.
• Eight TTL/LVDS configurable auxiliary outputs (exposure, synchronization, or
user output). See Matrox Helios hardware reference for supported configurations.
• Internal video generator for diagnostics.
1. Depends on version and revision of the board.
Board summary
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