Matrox Helios Series Installation And Hardware Reference page 147

Pin Signal
84 P3_LVDS_HSYNC_IN-
85 P3_LVDS_AUX(VSYNC)_IN+
86 P3_LVDS_AUX(VSYNC)_IN-
87 P3_LVDS_AUX(CLK)_OUT+
88 P3_LVDS_AUX(CLK)_OUT-
89 P3_LVDS_CLK_IN+
90 P3_LVDS_CLK_IN-
91 P3_LVDS/TTL_AUX(HSYNC)_OUT0+
92 P3_LVDS/TTL_AUX(HSYNC)_OUT0-
93 P3_LVDS/TTL_AUX(VSYNC)_OUT1+
94 P3_LVDS/TTL_AUX(VSYNC)_OUT1-
95 P3_LVDS/TTL_AUX(EXP)_OUT2+
96 P3_LVDS/TTL_AUX(EXP)_OUT2-
97 P3_LVDS/TTL_AUX(EXP)_OUT3+
98 P3_LVDS/TTL_AUX(EXP)_OUT3-
99 P3_TTL_AUX(TRIG)_IO
100 GND
Description
HSYNC input for acq. path 3, in LVDS format (negative).
LVDS auxiliary input for acq. path 3 (positive).
Supported signals: user input 0, trigger input 0, or VSYNC input (main purpose).
LVDS auxiliary input for acq. path 3 (negative).
See pin 85 for more information.
LVDS auxiliary output for acq. path 3 (positive).
Supported signals: user output 0 or clock output (main purpose).
LVDS auxiliary output for acq. path 3 (negative).
See pin 87 for more information.
Clock input for acq. path 3, in LVDS format (positive).
Clock input for acq. path 3, in LVDS format (negative).
LVDS/TTL auxiliary output 0 for acq. path 3 (positive).
Supported signals: HSYNC output (main purpose) or user output 1.
Negative component when LVDS signal arriving on LVDS/TTL auxiliary output 0 for acq. path 3.
See pin 91 for more information.
LVDS/TTL auxiliary output 1 for acq. path 3 (positive).
Supported signals: VSYNC output (main purpose) or user output 2.
Negative component when LVDS signal arriving on LVDS/TTL auxiliary output 1 for acq. path 3.
See pin 93 for more information.
LVDS/TTL auxiliary output 2 for acq. path 3 (positive).
Supported signals: exposure output 0 (main purpose) or user output 3.
Negative component when LVDS signal arriving on LVDS/TTL auxiliary output 2 for acq. path 3.
See pin 95 for more information.
LVDS/TTL auxiliary output 3 for acq. path 3 (positive).
Supported signals: exposure output 1 (main purpose) or user output 4.
Negative component when LVDS signal arriving on LVDS/TTL auxiliary output 3 for acq. path 3.
See pin 97 for more information.
TTL auxiliary input/output for acq. path 3.
Supported signals: trigger input 1 (main purpose), user input 3, or user output 5.
Ground
You can use the open-ended Matrox DBHD100-TO-OPEN cable to interface
with this connector. This cable has a 100-pin low-profile IDC connector at one
end, and open-ended wires at the other end.
Connectors on Matrox Helios eD/XD 147