Matrox Helios Series Installation And Hardware Reference page 82

82 Chapter 4: Matrox Helios hardware reference
Clock
Trigger signals
Trigger format
To establish which pixels are active in a line (because the horizontal
synchronization signal does not identify the blanking portion of the signal), the
board can generate a data valid signal based on information specified in the DCF.
Alternatively, you can define an auxiliary input signal as a data valid signal.
Each PSG can accept or provide one pixel clock signal (slave or master mode).
Each PSG accepts two external trigger inputs: one TTL or opto-isolated trigger
input and another LVDS or opto-isolated trigger input. For each PSG, you can
also program two path-independent auxiliary signals as trigger inputs; these can
be received in LVDS or TTL.
Each PSG can operate in one of the two following trigger modes; the mode is
specified by the DCF:
• Next valid frame/field mode. In this mode, the board waits for the next valid
frame or field (as specified by the DCF file) before commencing the grab. This
trigger mode functions in one of three ways:
- Edge-triggered monoshot acquisition. The board waits for the rising/falling
edge to capture a single frame.
- Edge-triggered continuous acquisition. The board waits for the rising/falling
edge to start a continuous grab.
- Level-sensitive continuous acquisition. The board grabs continuously while
the level of the trigger is high/low.
The polarity of the active and inactive levels of the trigger signal is software
❖
programmable.
• Asynchronous reset mode. In this mode, the board resets the video source to begin
a new frame when the trigger signal is received.
When received in TTL format directly, the signal must have a maximum
amplitude of 5 V. A signal over 2 V is considered high, while anything less than
0.8 V is considered low; the transition of 0.8 V to 2 V is considered to be the rising
edge.