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60 Chapter 4: Matrox Helios hardware reference
DB-44
connectors
connectors
(0 and 1)
1.
2.
3. Dependency on acquisition path is not illustrated.
In addition, Matrox Helios eA/XA has a comprehensive set of general purpose I/O
and serial ports to control video sources and other devices.
LVDS/TTL
Aux In(8)
drivers and
Aux Out(8)
receivers
and
DB-9
1,3
Opto-
Aux In(4)
couplers
Independent
acquisition
path 0
DVI
Independent
acquisition
path 1
Independent
acquisition
path 2
Independent
acquisition
path 3
On a separate bracket.
Refer to the "Synchronization and control signals" section for details.
Refer to the "Synchronization and control signals" section.
Performance
The video timing parameters supported by the board are as follows:
Number of pixels / line (including sync and blanking)
Number of lines / frame (including sync and blanking)
Pixel clock for single sampling rate operation
Pixel clock for double sampling rate operation
Analog bandwidth (-3 db cutoff frequency)
VID_IN
Attenuator,
A
Input
DC
Selector
restoration
B
Hsync/Csync
(LVDS/TTL)
Vsync (LVDS/TTL)
Clock (LVDS/TTL)
PSG
2
Aux In (TTL)
2
Aux Out (TTL)
Rx
RS-232
transceivers
Tx
Video
to
PCI-X
Bridge
Acquisition section of Matrox Helios eA/XA
Maximum
2 M
1 M
80 MHz
160 MHz
140 MHz
Low
offset,
10
10-bit
pass
LUTs
and
A/D
filter
gain
UART
Independent
acquisition
16
path
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