Matrox Helios Series Installation And Hardware Reference page 142

142 Appendix B: Technical information
Pin Signal
46 P0_LVDS/TTL_AUX(EXP)_OUT2-
47 P0_LVDS/TTL_AUX(EXP)_OUT3+
48 P0_LVDS/TTL_AUX(EXP)_OUT3-
49 P0_TTL_AUX(TRIG)_IO
50 GND
51 P1_LVDS_DATA_IN0+
52 P1_LVDS_DATA_IN0-
53 P1_LVDS_DATA_IN1+
54 P1_LVDS_DATA_IN1-
55 P1_LVDS_DATA_IN2+
56 P1_LVDS_DATA_IN2-
57 P1_LVDS_DATA_IN3+
58 P1_LVDS_DATA_IN3-
59 P1_LVDS_DATA_IN4+
60 P1_LVDS_DATA_IN4-
61 P1_LVDS_DATA_IN5+
62 P1_LVDS_DATA_IN5-
63 P1_LVDS_DATA_IN6+
64 P1_LVDS_DATA_IN6-
65 P1_LVDS_DATA_IN7+
66 P1_LVDS_DATA_IN7-
67 P1_LVDS_DATA_IN8+
68 P1_LVDS_DATA_IN8-
69 P1_LVDS_DATA_IN9+
70 P1_LVDS_DATA_IN9-
71 P1_LVDS_DATA_IN10+
72 P1_LVDS_DATA_IN10-
73 P1_LVDS_DATA_IN11+
74 P1_LVDS_DATA_IN11-
75 P1_LVDS_DATA_IN12+
Description
Negative component when LVDS signal arriving on LVDS/TTL auxiliary output 2 for acq. path 0.
See pin 45 for more information.
LVDS/TTL auxiliary output 3 for acq. path 0 (positive).
Supported signals: exposure output 1 (main purpose) or user output 4.
Negative component when LVDS signal arriving on LVDS/TTL auxiliary output 3 for acq. path 0.
See pin 47 for more information.
TTL auxiliary input/output for acq. path 0.
Supported signals: trigger input 1 (main purpose), user input 3, or user output 5.
Ground
Data bit 0 for acq. path 1, in LVDS format (positive).
Data bit 0 for acq. path 1, in LVDS format (negative).
Data bit 1 for acq. path 1, in LVDS format (positive).
Data bit 1 for acq. path 1, in LVDS format (negative).
Data bit 2 for acq. path 1, in LVDS format (positive).
Data bit 2 for acq. path 1, in LVDS format (negative).
Data bit 3 for acq. path 1, in LVDS format (positive).
Data bit 3 for acq. path 1, in LVDS format (negative).
Data bit 4 for acq. path 1, in LVDS format (positive).
Data bit 4 for acq. path 1, in LVDS format (negative).
Data bit 5 for acq. path 1, in LVDS format (positive).
Data bit 5 for acq. path 1, in LVDS format (negative).
Data bit 6 for acq. path 1, in LVDS format (positive).
Data bit 6 for acq. path 1, in LVDS format (negative).
Data bit 7 for acq. path 1, in LVDS format (positive).
Data bit 7 for acq. path 1, in LVDS format (negative).
Data bit 8 for acq. path 1, in LVDS format (positive).
Data bit 8 for acq. path 1, in LVDS format (negative).
Data bit 9 for acq. path 1, in LVDS format (positive).
Data bit 9 for acq. path 1, in LVDS format (negative).
Data bit 10 for acq. path 1, in LVDS format (positive).
Data bit 10 for acq. path 1, in LVDS format (negative).
Data bit 11 for acq. path 1, in LVDS format (positive).
Data bit 11 for acq. path 1, in LVDS format (negative).
Data bit 12 for acq. path 1, in LVDS format (positive).