Matrox Helios Series Installation And Hardware Reference page 109

• Acquisition paths can be combined to acquire from:
- Four single-tap 8 to 16-bit or dual-tap 8-bit monochrome sources.
- Two dual-tap 10 to 16-bit or four-tap 8-bit monochrome sources.
- One four-tap 10 to 16-bit or eight-tap 8-bit monochrome source.
- Two 8-bit RGB sources.
- One 10 to 16-bit RGB source.
• Four 256-entry 8-bit programmable lookup tables (LUTs) and four 4096 entry
8- or 16-bit LUTs.
• Supports frame and line-scan video sources.
• 128 MB/256 MB/512 MB/1 GB Mbytes of 167 MHz DDR SDRAM main
memory. Over 5.0 Gbytes/sec of memory bandwidth.
• Eight LVDS/RS-422 configurable auxiliary inputs (trigger, field polarity, data
valid, timer clock, and/or user input). All can be TTL. See Matrox Helios hardware
reference for supported configurations.
• Internal video generator for diagnostics.
• 8 Mbytes flash EEPROM.
Note that EEPROM is limited to 10000 write cycles.
❖
• Supports a x4 PCIe Host interface for Matrox Helios eD; supports a 64-bit
66/100/133 MHz 3.3 V PCI-X (or a 64-bit 33/66 MHz 3.3 V or 5 V
conventional PCI) Host interface for Matrox Helios XD.
• Integrated Watchdog circuitry for automatically recovering from application or
system failure.
• Supports an external rotary encoder with quadrature output.
1. Depending on revision of the board.
Board summary
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