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Trigger format
Exposure
- Level-sensitive continuous acquisition. The board grabs continuously while
the level of the trigger is high/low.
The polarity of the active and inactive levels of the trigger signal is software
❖
programmable.
• Asynchronous reset mode. In this mode, the board resets the video source to begin
a new frame when the trigger signal is received.
When received in TTL format directly, the signal must have a maximum
amplitude of 5 V. A signal over 2 V is considered high, while anything less than
0.8 V is considered low; the transition of 0.8 V to 2 V is considered to be the rising
edge.
If using the trigger to start acquisition, the trigger signal's pulse width must be
greater than two pixels; if using the trigger to start the exposure timer, the trigger
signal's pulse width must be greater than two clock periods of the timer. To
determine the timer period, take the inverse of the pixel or timer's clock frequency,
respectively. For example, if the pixel frequency is 12.27 MHz, the minimum pulse
width is 2 x 1/12.27 MHz (approximately 164 nsec).
The opto-isolated trigger signals pass through an opto-coupler. The voltage
difference across the positive and negative components of the signal must be
between 4.06 V and 9.165 V for logic high, and between -5.0 V and 0.8 V for
logic low.
Each PSG has two exposure timers. These timers can each generate two periodic
exposure output signals to control the exposure time and other external events
related to the video source. The exposure signals can be output as control signals
on the video input Camera Link connectors; they can also be output using
auxiliary output signals.
The timers can use a clock that is internally generated or one from an external
source. In the latter case, you can define an auxiliary signal as the clock source
(timer clock input).
Matrox Helios eCL/XCL acquisition section
57
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