Matrox Helios Series Installation And Hardware Reference page 71

Clock
Important
Trigger signals
Each PSG can accept or provide one pixel clock signal (slave or master mode).
When accessed from the analog video input connectors (DVI), the pixel clock,
composite/horizontal synchronization, and vertical synchronization signals of
each PSG form a group of signals. The signals of each group shares the same
direction (input or output) and same signal format (TTL or LVDS). When
accessed from the internal or external auxiliary I/O connectors (HD-44), the
format and direction of the synchronization signals are independent; the board
can both transmit and receive synchronization signals at the same time.
Each PSG accepts two external trigger inputs: one TTL or LVTTL trigger input
and another trigger input that passes through an opto-coupler, a device that
protects the board from outside surges. For each PSG, you can also program two
path-independent auxiliary signals as trigger inputs; these can be received in
LVDS, TTL, or LVTTL.
Each PSG can operate in one of the two following trigger modes; the mode is
specified by the DCF:
• Next valid frame/field mode. In this mode, the board waits for the next valid
frame or field (as specified by the DCF file) before commencing the grab. This
trigger mode functions in one of three ways:
- Edge-triggered monoshot acquisition. The board waits for the rising/falling
edge to capture a single frame.
- Edge-triggered continuous acquisition. The board waits for the rising/falling
edge to start a continuous grab.
- Level-sensitive continuous acquisition. The board grabs continuously while
the level of the trigger is high/low.
The polarity of the active and inactive levels of the trigger signal is software
❖
programmable.
• Asynchronous reset mode. In this mode, the board resets the video source to begin
a new frame when the trigger signal is received.
Matrox Helios eA/XA acquisition section 71