Agilent Technologies E8285A Manual page 251

Block Diagrams
Signal Flow and Interconnections
Table 8-1 Block Diagrams
Figure
Figure 8-1, "Signal Flow and Interconnections," on page 252
Figure 8-2, "RF I/O," on page 254
Figure 8-3, "Downconverter," on page 257
Figure 8-4, "Receiver Synthesizer," on page 258
Figure 8-5, "Receiver," on page 259
Figure 8-6, "Digital Cellsite 1 & 2," on page 260
Figure 8-7, "Analog Cell Site (FW Rev A.04.54 and below)," on page 261
Figure 8-8, "Analog Cell Site (FW Rev A.05.03 and above)," on page 262
Figure 8-9, "Protocol Processor," on page 263
Figure 8-10, "Spectrum Analyzer," on page 265
Figure 8-11, "Audio Analyzer 1," on page 267
Figure 8-12, "Audio Analyzer 2," on page 268
Figure 8-13, "Measurement Board," on page 269
Figure 8-14, "Signaling and Analyzer Assembly," on page 270
Figure 8-15, "IQ Modulator," on page 272
Figure 8-16, "LO/IF/Demodulator," on page 273
Figure 8-17, "Digital Signal Processor 1 (DSP1)," on page 274
Figure 8-18, "CDMA Reference," on page 276
Figure 8-19, "Signaling and Analyzer Assembly," on page 277
Figure 8-20, "Modulation Distribution," on page 278
Figure 8-21, "Signal Generator Synthesizer," on page 281
Figure 8-22, "RF Output Section," on page 282
Figure 8-23, "Upconverter," on page 283
Figure 8-24, "High Stability Reference," on page 285
Figure 8-25, "Regulator," on page 286
Figure 8-26, "Memory SBRC," on page 288
Figure 8-27, "Controller," on page 289
Figure 8-28, "Display Driver," on page 290
Figure 8-29, "GPIB/Serial," on page 291
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