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UG-438
Table 31. HDMI Flags in IO Map Register 0x7E
Bit Name
NEW_GAMUT_MDATA_RAW
AUDIO_PCKT_ERR_RAW
PACKET_ERROR_RAW
CHANGE_N_RAW
CTS_PASS_THRSH_RAW
FIFO_OVERFLO_RAW
FIFO_UNDERFLO_RAW
FIFO_NEAR_OVFL_RAW
Table 32. HDMI Flags in IO Map Register 0x83
Bit Name
FIFO_NEAR_UFLO_RAW
NEW_TMDS_FRQ_RAW
AUDIO_FLT_LINE_RAW
NEW_SAMP_RT_RAW
PARITY_ERROR_RAW
AUDIO_MODE_CHNG_RAW
VCLK_CHNG_RAW
DEEP_COLOR_CHNG_RAW
Bit Position
Description
0 (LSB)
When set to 1 indicates that a gamut metadata packet with new content has been received.
Once set, this bit remains high until the interrupt is cleared via NEW_GAMUT_
MDATA_PCKT_CLR. (IO Map 0x80[0]).
1
When set to 1 indicates that an uncorrectable error was detected in the body of an audio
packet. Once set, this bit remains high until the interrupt is cleared via
AUDIO_PCKT_ERR_CLR (IO Map 0x80[1]).
2
When set to 1 it indicates an uncorrectable EEC error was detected in the body or header of
any packet. Once set, this bit remains high until the interrupt is cleared via
PACKET_ERROR_CLR (IO Map 0x80[2]).
3
When set to 1 it indicates the N value of the ACR packets has changed. Once set, this bit
remains high until the interrupt is cleared via CHANGE_N_CLR (IO Map 0x80 [3]).
4
When set to 1 it indicates the CTS value of the ACR packets has exceeded the threshold set
by CTS_CHANGE_THRESHOLD. Once set, this bit remains high until the interrupt is cleared
via CTS_PASS_THRSH_CLR (IO Map 0x80[4]).
5
When set to 1 it indicates the audio FIFO write pointer has reached the read pointer causing
the audio FIFO to overflow. Once set, this bit remains high until the interrupt is cleared via
FIFO_OVERFLO_CLR (IO Map 0x80[5]).
6
When set to 1 it indicates the audio FIFO read pointer has reached the write pointer causing
the audio FIFO to underflow. Once set, this bit remains high until the interrupt is cleared via
FIFO_UNDERFLO_CLR (IO Map 0x80[6]).
7 (MSB)
When set to 1 it indicates the audio FIFO is near overflow as the number FIFO registers
containing stereo data is greater or equal to value set in AUDIO_FIFO_ALMOST_FULL_
THRESHOLD. Once set, this bit remains high until the interrupt is cleared via
FIFO_NEAR_OVFL_CLR (IO Map 0x80[7]).
Bit Position
Description
0 (LSB)
When set to 1 it indicates the audio FIFO is near underflow as the number of FIFO registers
containing stereo data is less or equal to value set in AUDIO_FIFO_ALMOST_EMPTY_
THRESHOLD. Once set, this bit remains high until the interrupt is cleared via
FIFO_NEAR_UFLO_CLR (IO Map 0x85[0]).
1
When set to 1 it indicates the TMDS frequency has changed by more than the tolerance set
in FREQTOLERANCE[3:0] Once set, this bit remains high until the interrupt is cleared via
NEW_TMDS_FREQ_CLR (IO Map 0x85[1]).
2
When set to 1 it indicates audio sample packet has been received with the flat line bit set to
1. Once set, this bit remains high until the interrupt is cleared via AUDIO_FLT_LINE_
CLR (IO Map 0x85[2]).
3
When set to 1 it indicates that audio sampling frequency field in channel status data has
changed. Once set, this bit remains high until the interrupt is cleared via NEW_SAMP_
RT_CLR (IO Map 0x85[3]).
4
When set to 1 it indicates an audio sample packet has been received with parity error. Once
set, this bit remains high until the interrupt is cleared via PARITY_ERROR_CLR (IO Map 0x85
[4]).
5
When set to 1 it indicates that the type of audio packet received has changed. The following
are considered audio modes, no audio, PCM, DSD, HBR, or DST. AUDIO_SAMPL_PCKT_DET,
DSD_PACKET_DET, DST_AUDIO_PCKT_DET, and HBR_AUDIO_PCKT_DET used identify type
of audio packet currently received. Once set, this bit remains high until the interrupt is
cleared via AUDIO_MODE_CHNG_CLR (IO Map 0x85[5]).
6
When set to 1 it indicates that irregular or missing pulses are detected in the TMDS clock.
Once set, this bit remains high until the interrupt is cleared via VCLK_CHNG_CLR (IO Map
0x85[6]).
7 (MSB)
When set to 1 it indicates a change in the deep color mode has been detected. Once set, this
bit remains high until the interrupt is cleared via DEEP_COLOR_CHNG_CLR (IO Map 0x85[7]).
Rev. 0 | Page 90 of 184
Hardware User Guide
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