Tmds Equalization; Port Selection; Tmds Clock Activity Detection - Analog Devices ADV7610 Hardware User's Manual

Hardware User Guide
Notes
•
After EDID_A_ENABLE
address locations 0x7F, 0xFF, 0X17F, and 0x1FF in the internal EDID RAM with the computed checksums.
•
After power up, the ADV7610
is recommended to wait for at least 1 ms before initializing the EDID map with E-EDID.
•
When internal E-EDID is enabled on Port A, the hot plug should not be asserted until the EDID map has been completely initialized
with E-EDID.
•
The internal E-EDID can be accessed in read-only mode through the DDC interface at the I
•
The internal E-EDID can be accessed in read/write mode through the general I

TMDS EQUALIZATION

The ADV7610 incorporates active equalization of the HDMI data signals. This equalization compensates for the high frequency losses
inherent in HDMI and DVI cabling, especially at long lengths and higher frequencies. The
lengths up to 30 meters and for pixel clock frequencies up to 225 MHz.

PORT SELECTION

HDMI_PORT_SELECT allows the selection of the active HDMI port. The only port on
HDMI_PORT_SELECT[2:0], Addr 68 (HDMI), Address 0x00[2:0]
This two bit control is used for HDMI primary port selection.
Function
HDMI_PORT_SELECT[2:0]
000 (default)

TMDS CLOCK ACTIVITY DETECTION

The ADV7610 provides circuitry to monitor TMDS clock activity on HDMI port. The firmware can poll the appropriate registers for
TMDS clock activity detection and configure the
detects activity above 25 MHz on the TMDS clock input.
PORT A E-EDID STRUCTURE
0x1FF
0x180
0x17F
0x100
0xFF
0x80
0x7F
0x00
Figure 4. Port A E-EDID Structure and Mapping for SPA Located in EDID Block 1
is set to 1, the ADV7610 EDID/repeater controller computes the checksums and updates the internal RAM
E-EDID controller sets all bytes in the internal EDID RAM to 0, this operation takes less than 1 ms. It
Description
Port A
ADV7610
BLOCK 2 CHECKSUM
0x1FE
BLOCK 3
BLOCK 2 CHECKSUM
0x17E
BLOCK 2
BLOCK 1 CHECKSUM
0xFE
BLOCK 1
BLOCK 0 CHECKSUM
0x7E
BLOCK 0
2 C interface at the EDID map I
as desired. TMDS clock detection control is active as soon as the
Rev. 0 | Page 31 of 184
2 C address 0xA0.
2 C address.
ADV7610 is capable of equalizing for cable
ADV7610 is Port A.
UG-438
ADV7610