Hdmi Receiver; +5 V Cable Detect - Analog Devices ADV7610 Hardware User's Manual

UG-438

HDMI RECEIVER

HPA_A/INT2
RXA_5V
CEC
DDCA_SDA/DDCA_SCL
RXA_C±
RXA_0±
EQUALIZER
RXA_1±
RXA_2±

+5 V CABLE DETECT

The HDMI receiver in the ADV7610
can be read back from the following I
CABLE_DET_A_RAW, IO, Address 0x6F[0] (Read Only)
Raw status of Port A +5 V cable detection signal.
Function
CABLE_DET_A_RAW
0 (default)
1
The ADV7610 provides a digital glitch filter on the +5 V power signals from the HDMI port. The output of this filter is used to reset the
HDMI block (refer to the HDMI Section Reset Strategy section).
The +5 V power signal must be constantly high for the duration of the timer (controlled by FILT_5V_DET_TIMER[6:0]), otherwise the
output of the filter is low. The output of the filter returns low as soon as any change in the +5 V power signal is detected.
FILT_5V_DET_DIS, Addr 68 (HDMI), Address 0x56[7]
This control is used to disable the digital glitch filter on the HDMI 5 V detect signals. The filtered signals are used as interrupt flags and
used to reset the HDMI section. The filter works from an internal ring oscillator clock and, therefore, is available in power-down mode.
The clock frequency of the ring oscillator is 42 MHz ± 10%.
Function
FILT_5V_DET_DIS
0 (default)
1
Note: If the +5 V pins are not used and are left unconnected, the +5 V detect circuitry must be disconnected from the HDMI reset signal
by setting DIS_CABLE_DET_RST
5V DETECT
AND HPA
CONTROLLER
CEC
CONTROLLER
EDID/
REPEATER
CONTROLLER
HDCP
EEPROM
HDCP
PLL
BLOCK
SAMPLER
Figure 3. Functional Block Diagram of HDMI Core
can monitor the level on the +5 V power signal pin of the HDMI port. The results of this detection
2 C registers. These readbacks are valid even when the part is not configured for HDMI mode.
Description
No cable detected on Port A
Cable detected on Port A (high level on RXA_5V)
Description
Enabled
Disabled
to 1. This avoids holding the HDMI section in reset.
DEEP COLOR
CONVERSION
DATA
HS
4:2:2 TO 4:4:4
VS
CONVERSION
DE
FILTER
PACKET/
INFOFRAME
MEMORY
PACKET
PROCESSOR
Rev. 0 | Page 26 of 184
Hardware User Guide
TO INTERRUPT
CONTROLLER
TO DPP
TO DPP
TO DPP
TO DPP
I2S0 TO I2S3
SCLK/INT2
MCLK/INT2
AUDIO
PROCESSOR