Hardware User Guide
CHANNEL A
LSB
MSB
FRAME N
DSD Audio Interface and Output Controls
The
ADV7610
incorporates a four DSD channel interface used to output the audio stream extracted from DSD packets. Each of the DSD
channels carries an oversampled 1-bit representation of the audio signal as delivered on SACDs.
Table 12. DSD Interface Description
DSD Interface IO
DSD0A
DSD0B
DSD1A
DSD1B
SCLK
MCLKOUT
Two controls are provided to change the mapping between the audio output ports and DSD signals.
DSD_MAP_ROT[2:0], Addr 68 (HDMI), Address 0x6D[2:0]
A control to select the arrangement of the DSD interface on the audio output port pins.
Function
DSD_MAP_ROT[2:0]
Description
000 (default)
Reserved
001
DSD0A on I2S0, DSD0B on I2S1, DSD1A on I2S2, DSD1B on I2S3
010
DSD0A on I2S1, DSD0B on I2S2, DSD1A on I2S3, DSD1B on LRCLK
011 to 111
Reserved
DSD_MAP_INV, Addr 68 (HDMI), Address 0x6D[3]
A control to invert the arrangement of the DSD interface on the audio output port pins. Note the arrangement of the DSD interface on
the audio output port pins is determined by DSD_MAP_ROT[2:0].
Function
DSD_MAP_INV
Description
0 (default)
Do not invert arrangement of the DSD channels on the audio output port pins
1
Invert arrangement of the DSD channels on the audio output port pins
Note that DSD0A and DSD0B output must be used when in stereo mode only. DSD0A and DSD0B always carry the main 2-channel
audio data. DSD1A and DSD1B are the surround channels where: xx is the channel, for example, 0A, 0B.
By default, the
ADV7610
automatically enables the DSD interface if it receives DSD packets. The
I
S interface if it receives audio sample packets or if it does not receive any audio packets. However, it is possible to override the audio
2
interface that is used via the
V
U
C
B
32 CLOCK SLOTS
Figure 19. AES3 Stream Timing Diagram
SCLK
DSDxx
Figure 20. DSD Timing Diagram
OVR_AUTO_MUX_DSD_OUT
CHANNEL B
LSB
MSB
V
32 CLOCK SLOTS
Function
First DSD data channel
Second DSD data channel
Third DSD data channel
Fourth DSD data channel
Bit clock
Audio master clock output
and
MUX_DSD_OUT
controls.
Rev. 0 | Page 55 of 184
U
C
B
ADV7610
also automatically enables the
UG-438
FRAME N + 1
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