Cp Output Synchronization Signal Positioning - Analog Devices ADV7610 Hardware User's Manual

UG-438
Note: Although the two points for VGA72 and VGA75 look very close, it is anticipated that the difference in the parameters is sufficient
to distinguish between them.

CP OUTPUT SYNCHRONIZATION SIGNAL POSITIONING

The ADV7610 overall synchronization processing flow is shown in the block diagram in Figure 47. The user can reposition the
synchronization signal output from the regenerated input synchronization signal within the CP block with the control bits marked in red
in Figure 10.
HDMI PORT A
1200
1000
800
600
400
200
0
0 2000
28.6363MHz SAMPLES IN 8-LINE BLOCK
Figure 46. STDI Values for GR Mode (Plot)
PRIM_MODE[2]
HDMI PIXEL CLOCK
HDMI BLOCK
HS
VS
TMDS
PLL
STDI 1
Figure 47. ADV7610 Simplified Synchronization Signal Processing Flow Diagram
VGA 72
VGA 75
4000 6000
0
1
SYNC POSITION
CONTROL
OUTPUT
CONTROL
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Hardware User Guide
8000
START_HS, END_HS
START_VS, END_VS
DE_H_END, DE_H_S TART
DE_V_START, DE_V_END
DE_V_START_EVEN, DE_V_END_EVEN
START_VS_EVEN, END_VS_EVEN
START_FE, START_FO
COMPONENT
PROCESSOR
HS
POLARITY
VS
CONTROL
DE
LLC
HS
VS
DE