Analog Devices ADV7610 Hardware User's Manual page 35

Hardware User Guide
TMDS
CLOCK
TMDS
CHANNEL 0
TMDS
CHANNEL 1
TMDS
CHANNEL 2
The video FIFO is designed to operate completely autonomously. It automatically resynchronizes the read and write pointers if they are
about to point to the same location. However, it is also possible for the user to observe and control the FIFO operation with a number of
FIFO status and control registers.
DCFIFO_LEVEL[2:0], Addr 68 (HDMI), Address 0x1C[2:0] (Read Only)
A readback that indicates the distance between the read and write pointers. Overflow/underflow would read as Level 0. Ideal centered
functionality would read as 0b100.
Function
DCFIFO_LEVEL[2:0]
000 (default)
001
010
011
100
101
110
111
DCFIFO_LOCKED, Addr 68 (HDMI), Address 0x1C[3] (Read Only)
A readback to indicate if video FIFO is locked.
Function
DCFIFO_LOCKED
0 (default)
1
DCFIFO_RECENTER, Addr 68 (HDMI), Address 0x5A[2] (Self-Clearing)
A reset to recenter the video FIFO. This is a self-clearing bit.
Function
DCFIFO_RECENTER
0 (default)
1
TMDS
PLL
TMDS CH0
10
TMDS
SAMPLING
TMDS CH1
AND
DATA
10
RECOVERY
TMDS CH2
10
Figure 5. HDMI Video FIFO
Description
FIFO has underflowed or overflowed.
FIFO is about to overflow.
FIFO has some margin.
FIFO has some margin.
FIFO perfectly balanced
FIFO has some margin.
FIFO has some margin.
FIFO is about to underflow.
Description
Video FIFO is not locked. Video FIFO had to resynchronize between previous two VSyncs.
Video FIFO is locked. Video FIFO did not have to resynchronize between previous two VSyncs.
Description
Video FIFO normal operation
Video FIFO to recenter
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DIVIDER
R
12
G
12
B
TMDS
12
DECODING
HS
VS
DE
UG-438
DPLL
R
12
G
12
B
FIFO
12
HS
VS
DE