Analog Devices ADV7610 Hardware User's Manual page 54

UG-438
LEFT
MSB
LEFT
MSB
0
SYNC
PREAMBLE
0
L
S
B
MSB MSB MSB MSB – 1
MSB EXTENDED
32 CLOCK SLOTS
Figure 15. Timing Audio Data Output in Right Justified Mode
LSB
32 CLOCK SLOTS
Figure 16. Timing Audio Data Output in Left Justified Mode
3 4
L
S
B
Figure 17. IEC60958 Subframe Timing Diagram
DATA
Figure 18. AES3 Subframe Timing Diagram
RIGHT
LSB MSB MSB MSB
MSB EXTENDED
32 CLOCK SLOTS
RIGHT
MSB
32 CLOCK SLOTS
AUDIO SAMPLE WORD
VALIDITY FLAG
USER DATA
CHANNEL STATUS
PARITY BIT
23 24
M
V
S
B
VALIDITY FLAG
USER DATA
CHANNEL STATUS
BLOCK START FLAG
Rev. 0 | Page 54 of 184
Hardware User Guide
MSB MSB – 1 LSB
LSB
27 28 31
M
V U C P
S
B
27 31
U C B 0 0 0 0
ZERO PADDING