Interrupts; Interrupt Architecture Overview - Analog Devices ADV7610 Hardware User's Manual

Hardware User Guide

INTERRUPTS

INTERRUPT ARCHITECTURE OVERVIEW

The ADV7610 interrupt architecture provides four different types of bits, namely
•
Raw bits
•
Status bits
•
Interrupt mask bits
•
Clear bits
Raw bits are defined as being either edge-sensitive or level-sensitive. The following example compares AVI_INFO_RAW and
NEW_AVI_INFO_RAW to demonstrate the difference.
AVI_INFO_RAW, IO, Address 0x60[0] (Read Only)
Raw status of AVI InfoFrame detected signal. This bit is set to one when an AVI InfoFrame is received and is reset to zero if no AVI
InfoFrame is received for more than 7 VSyncs (on the eighth VSync leading edge following the last received AVI InfoFrame), after an
HDMI packet detection reset or upon writing to AVI_PACKET_ID.
Function
AVI_INFO_RAW Description
0 (default) No AVI InfoFrame has been received within the last seven VSyncs or since the last HDMI packet detection reset
1 An AVI InfoFrame has been received within the last seven VSyncs
NEW_AVI_INFO_RAW, IO, Address 0x79[0] (Read Only)
Status of the new AVI InfoFrame interrupt signal. When set to 1, it indicates that an AVI InfoFrame has been received with new contents.
Once set, this bit will remain high until the interrupt is cleared via NEW_AVI_INFO_CLR.
Function
NEW_AVI_INFO_RAW Description
0 (default) No new AVI InfoFrame received
1 AVI InfoFrame with new content received
In the case of AVI_INFO_RAW, this bit always represents the current status of whether or not the part is receiving AVI InfoFrames. It is
not a latched bit and never requires to be cleared. This is the definition of a level-sensitive raw bit.
In the case of NEW_AVI_INFO_RAW the same strategy would not work. If the NEW_AVI_INFO_RAW bit were to behave in the same
way as AVI_INFO_RAW it would go high at the instant the new InfoFrame was received, and would go low again some clock cycles
afterwards. This is because a new InfoFrame is only new the instant it is received, and once received it no longer new, so the event to set
this bit only last for an instant and is then gone.
Having a raw bit that is only held high for an instant is not useful. Therefore, for these types of events, the raw bit is latched, and must be
cleared by the corresponding clear bit. Accordingly, the raw bit does not truly represent the current status; instead, it represents the status
of an edge event that happened in the past. This is the definition of an edge-sensitive raw bit.
All raw bits, with the exceptions of INTRQ_RAW and INTRQ2_RAW, have corresponding status bits. The status bits always work in the
same manner whether the raw bit is edge or level sensitive. Status bits have the following characteristics
•
A status bit must be enabled by setting either or both of the corresponding interrupt mask bits
•
Status bits are always latched, and must be cleared by the corresponding clear bit.
When either of the interrupt mask bits for a given interrupt is set, if that raw bit changes state the corresponding status bit goes high and
an interrupt is generated on the INT1 or INT2 pin, depending on which interrupt mask bit was set. The status bit must be cleared using
the appropriate clear bit. The status bits, interrupt mask bits, and clear bits for AVI_INFO and NEW_AVI_INFO are described here for
completeness.
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