Analog Devices ADV7610 Hardware User's Manual page 47

Hardware User Guide
Audio DPLL
The audio DPLL generates an internal audio master clock with a frequency of 128 times the audio sampling frequency, usually called fs.
The audio master clock is used to clock the audio processing section.
Locking Mechanism
When the upstream HDMI transmitter outputs a stable TMDS frequency and consistent audio clock regeneration values, the audio DPLL
locks within two cycles of the audio master clock after the following two conditions are met:
•
TMDS PLL is locked (refer to TMDS_PLL_LOCKED)
•
ADV7610 has received an ACR packet with N and CTS parameters within a valid range
The audio DPLL lock status can be monitored via AUDIO_PLL_LOCKED.
AUDIO_PLL_LOCKED, Addr 68 (HDMI), Address 0x04[0] (Read Only)
A readback to indicate the Audio DPLL lock status.
Function
AUDIO_PLL_LOCKED Description
0 (default) The audio DPLL is not locked.
1 The audio DPLL is locked.
ACR Parameters Loading Method
The N and CTS parameters from the ACR packets are used to regenerate the audio clock and are reloaded into the DPLL anytime they
change. The self-clearing bit
parameters from the ACR packet into the audio DPLL.
FORCE_N_UPDATE, Addr 68 (HDMI), Address 0x5A[0] (Self-Clearing)
A control to force an N and CTS value update to the audio DPLL. The audio DPLL regenerates the audio clock.
Function
FORCE_N_UPDATE Description
0 (default) No effect
1 Forces an update on the N and CTS values for audio clock regeneration
Audio DPLL Coast Feature
The audio DPLL incorporates a coast feature that allows it to indefinitely output a stable audio master clock when selectable events occur.
The coast feature allows the audio DPLL to provide an audio master clock when the audio processor mutes the audio following a mute
condition (refer to the Audio Muting section). The events that cause the audio DPLL to coast are selected via the coasts masks listed in
Table 8.
Table 8. Selectable Coast Conditions
HDMI Map
Bit Name Address
AC_MSK_VCLK_CHNG 0x13[6]
AC_MSK_VPLL_UNLOCK 0x13[5]
AC_MSK_NEW_CTS 0x13[3]
AC_MSK_NEW_N 0x13[2]
AC_MSK_CHNG_PORT
AC_MSK_VCLK_DET 0x13[0]
FORCE_N_UPDATE provides a means to reset the audio DPLL by forcing a reload of the N and CTS
Description
When set to 1, audio DPLL coasts if TMDS clock has any
irregular/missing pulses
When set to 1, audio DPLL coasts if TMDS PLL unlocks
When set to 1, audio DPLL coasts if CTS changes by more
than threshold set in
When set to 1, audio DPLL coasts if N changes
0x13[1] When set to 1, audio DPLL coasts if active port is changed
When set to 1, audio DPLL coasts if no TMDS clock is detected
on the active port
CTS_CHANGE_THRESHOLD[5:0]
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Corresponding Status
Register(s)
VCLK_CHNG_RAW
TMDS_PLL_LOCKED
CTS_PASS_THRSH_RAW
CHANGE_N_RAW
HDMI_PORT_SELECT[2:0]
TMDS_CLK_A_RAW