Analog Devices ADV7610 Hardware User's Manual page 164

UG-438
INTERRUPT_STATUS_6 register consists of fields: CP_LOCK_CH1_ST, CP_UNLOCK_CH1_ST, and STDI_DVALID_CH1_ST.
CP_LOCK_CH1_ST, IO, Address 0x5C[3] (Read Only)
Function
CP_LOCK_CH1_ST
0 (default)
1
CP_UNLOCK_CH1_ST, IO, Address 0x5C[2] (Read Only)
Function
CP_UNLOCK_CH1_ST
0 (default)
1
STDI_DVALID_CH1_ST, IO, Address 0x5C[1] (Read Only)
Latched signal status of STDI valid for Sync Channel 1 interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
STDI_DATA_VALID_CH1_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
STDI_DVALID_CH1_ST
0 (default)
1
HDMI Lvl INT Status 1 register consists of fields: ISRC2_PCKT_ST, ISRC1_PCKT_ST, ACP_PCKT_ST, VS_INFO_ST, MS_INFO_ST,
SPD_INFO_ST, and AUDIO_INFO_ST.
ISRC2_PCKT_ST, IO, Address 0x61[7] (Read Only)
Latched status of ISRC2 packet detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
ISRC2_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
ISRC2_PCKT_ST
0 (default)
1
ISRC1_PCKT_ST, IO, Address 0x61[6] (Read Only)
Latched status of ISRC1 packet detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
ISRC1_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
ISRC1_PCKT_ST
0 (default)
1
ACP_PCKT_ST, IO, Address 0x61[5] (Read Only)
Latched status of audio content protection packet detected interrupt signal. Once set, this bit will remain high until the interrupt is
cleared via ACP_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
ACP_PCKT_ST
0 (default)
1
Description
No change. An interrupt has not been generated from this register.
Channel 1 CP input has caused the decoder to go from an unlocked state to a locked state.
Description
No change. An interrupt has not been generated from this register.
Channel 1 CP input has changed from a locked state to an unlocked state and has triggered an interrupt.
Description
No STDI valid for sync Channel 1 interrupt has occurred.
A STDI valid for sync Channel 1 interrupt has occurred.
Description
No interrupt generated from this register.
ISRC2_PCKT_RAW has changed. Interrupt has been generated.
Description
No interrupt generated from this register.
ISRC1_PCKT_RAW has changed. Interrupt has been generated.
Description
No interrupt generated from this register.
ACP_PCKT_RAW has changed. Interrupt has been generated.
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Hardware User Guide