Analog Devices ADV7610 Hardware User's Manual page 12

UG-438
CORE_PDN
CORE_PDN allows the user to power down clocks, with the exception of the XTAL clock, in the following sections:
•
CP block
•
Digital section of the HDMI block
CORE_PDN, IO, Address 0x0B[1]
A power-down control for the DPP, CP core, and digital sections of the HDMI core.
Function
CORE_PDN
0 (default)
1
Power-Down Modes
The ADV7610 supports the following power-down modes:
•
Power-Down Mode 0
•
Power-Down Mode 1
Table 5 shows the power-down and normal modes of ADV7610.
Table 5. Power-Down Modes
POWER_DOWN Bit
0
0
1
1
1 Dependent on the values of EDID_X_ENABLE_CPU and EDID_X_ENABLE for the HDMI port (where X is A).
Power-Down Mode 0
In Power-Down Mode 0, selected sections and pads are kept active to provide EDID and +5 V antiglitch filter functionality.
In Power-Down Mode 0, the sections of the
•
I 2 C slave section.
•
EDID/repeater controller.
•
EDID ring oscillator.
The ring oscillator provides a clock to the EDID/repeater controller (refer to the E-EDID/Repeater Controller section) and the +5 V
power supply antiglitch filter. The clock output from the ring oscillator runs at approximately 50 MHz.
The following pads only are enabled in Power-Down Mode 0:
•
I 2 C pads
•
SDA
•
SCL
•
+5 V pads
•
RXA_5V
•
HPA_A
•
DDC pads
•
DDCA_SCL
•
DDCA_SDA
•
Reset pad RESET
Power-Down Mode 0 is initiated through a software (I
Description
Powers up CP and digital sections of HDMI block
Powers down CP and digital section of HDMI block
CEC_POWER_UP Bit
0
1
0
1
ADV7610 are disabled except for the following blocks:
C register) configuration.
2
Rev. 0 | Page 12 of 184
CEC EDID
Disabled Enabled
Enabled Enabled
Disabled Enabled
1
Enabled Enabled 1
Hardware User Guide
Power-Down Mode
Power-Down Mode 0
Power-Down Mode 1
Normal mode
Normal mode