Analog Devices ADV7610 Hardware User's Manual page 166

UG-438
AV_MUTE_ST, IO, Address 0x66[5] (Read Only)
Latched status of AV mute detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via AV_MUTE_CLR.
This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
AV_MUTE_ST
0 (default)
1
AUDIO_CH_MD_ST, IO, Address 0x66[4] (Read Only)
Latched status of audio channel mode interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
AUDIO_CH_MD_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
AUDIO_CH_MD_ST Description
0 (default) AUDIO_CH_MD_RAW has not changed. An interrupt has not been generated.
1 AUDIO_MODE_CHNG_RAW has changed. An interrupt has been generated.
HDMI_MODE_ST, IO, Address 0x66[3] (Read Only)
Latched status of HDMI mode interrupt signal. Once set, this bit will remain high until the interrupt is cleared via HDMI_MODE_CLR.
This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
HDMI_MODE_ST Description
0 (default) HDMI_MODE_RAW has not changed. An interrupt has not been generated.
1 (No Suggestions) has changed. An interrupt has been generated.
GEN_CTL_PCKT_ST, IO, Address 0x66[2] (Read Only)
Latched status of general control packet interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
GEN_CTL_PCKT_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
GEN_CTL_PCKT_ST Description
0 (default) GEN_CTL_PCKT_RAW has not changed. Interrupt has not been generated from this register.
1 GEN_CTL_PCKT_RAW has changed. Interrupt has been generated from this register.
AUDIO_C_PCKT_ST, IO, Address 0x66[1] (Read Only)
Latched status of audio clock regeneration packet interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
AUDIO_PCKT_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
AUDIO_C_PCKT_ST Description
0 (default) AUDIO_C_PCKT_RAW has not changed. Interrupt has not been generated from this register.
1 AUDIO_C_PCKT_RAW has changed. Interrupt has been generated from this register.
GAMUT_MDATA_ST, IO, Address 0x66[0] (Read Only)
Latched status of gamut metadata packet detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
GAMUT_MDATA_PCKT_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
GAMUT_MDATA_ST Description
0 (default) GAMUT_MDATA_RAW has not changed. Interrupt has not been generated from this register.
1 GAMUT_MDATA_RAW has changed. Interrupt has been generated from this register.
HDMI Lvl INT Status 3 register consists of fields: TMDSPLL_LCK_A_ST, TMDS_CLK_A_ST, VIDEO_3D_ST, V_LOCKED_ST, and
DE_REGEN_LCK_ST.
TMDSPLL_LCK_A_ST, IO, Address 0x6B[6] (Read Only)
Latched status of Port A TMDS PLL lock interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
TMDSPLL_LCK_A_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Description
AV_MUTE_RAW has not changed. An interrupt has not been generated.
AV_MUTE_RAW has changed. An interrupt has been generated.
Rev. 0 | Page 166 of 184
Hardware User Guide