Analog Devices ADV7610 Hardware User's Manual page 53

Hardware User Guide
Notes
•
I2SOUTMODE is effective when the
where the ADV7610 receives audio sample packets
•
The ADV7610 receives HBR packets, OVR_MUX_HBR is set to 1, and MUX_HBR_OUT is set to 2'b00, 2'b01, 2'b10 or 2'b11.
•
In HBR mode, it is required that the part outputs four SPDIF, I
word. Therefore, 12SBITWIDTH[4:0] must always be set to 0b11000.
The following audio formats can be output when the
•
L-PCM audio data is output on the audio output pins if the part receives the audio sample packets with L-PCM encoded audio data.
Each audio output pin carries stereo data that can be output in I
Figure 16). The I2SOUTMODE[1:0] control must be set to 0x0, 0x01, or 0x2 to output I
respectively, on the audio output pins.
•
A stream conforming to the IEC60958 specification when the part receives audio sample packets with L-PCM encoded data (refer to
Figure 17).
•
An AES3 stream if the I2SOUTMODE[1:0] control is set to 0x3 (refer to Figure 18 and Figure 19). Note that AES3 is also referred to
as raw SPDIF. Each AES3 stream may encapsulate stereo L-PCM audio data or multichannel non L-PCM audio data (for example,
5.1 Dolby Digital).
•
Binary stream on the audio output pins when the part receives audio sample packets with non L-PCM encoded audio data (that is,
AC-3 compressed audio) and if the following configuration is used:
•
I2SOUTMODE must be set to 0x0, 0x01, or 0x2 for I
and Figure 16).
•
MT_MSK_COMPRS_AUD is set to 0.
Note that no audio flags are output by the part in that configuration. Each binary stream output by the part may encapsulate stereo L-
PCM audio data or multichannel non L-PCM audio data (for example, 5.1 Dolby Digital).
Table 11. I 2 S/SPDIF Interface Description
I 2 S/SPDIF Interface IO
I2S0/SDPIF0
I2S1/SDPIF1
I2S2/SDPIF2
I2S3/SDPIF3
SCLK
LRCLK
MCLKOUT
LRCLK LEFT
SCLK
ISx
ADV7610 is configured to output I
ADV7610
Function
I 2 S audio (Channel 1, Channel 2)/SPDIF0
I 2 S audio (Channel 3, Channel 4)/SPDIF1
I 2 S audio (Channel 5, Channel 6)/SPDIF2
I 2 S audio (Channel 7, Channel 8)/SPDIF3
Bit clock
Data output clock for left and right channel
Audio master clock output
MSB LSB
32 CLOCK SLOTS
Figure 14. Timing Audio Data Output in I
S streams or AES3 streams. This is the case in the situation
2
2 S, or raw IEC60958 streams encapsulating a 24-bit audio sample
receives audio sample packets:
2 S, right justified, or left justified mode (see Figure 14, Figure 15, and
S, right justified, and left justified format, respectively (see Figure 14, Figure 15,
2
RIGHT
MSB
32 CLOCK SLOTS
2
S Mode
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S, right justified, and left justified
2
LSB
UG-438