Analog Devices ADV7610 Hardware User's Manual page 56

UG-438
OVR_AUTO_MUX_DSD_OUT, Addr 68 (HDMI), Address 0x01[3]
DSD/DST override control. In automatic control, DSD or I
interface is enabled if the part receives DSD or DST audio sample packet. I
or when no packet is received. In manual mode,
Function
OVR_AUTO_MUX_DSD_OUT
0 (default)
1
MUX_DSD_OUT, Addr 68 (HDMI), Address 0x01[4]
An override control for the DSD output.
Function
MUX_DSD_OUT
0 (default)
1
HBR Interface and Output Controls
The ADV7610 can receive HBR audio stream packets. The ADV7610 outputs HBR data over four of the audio output pins in any of the
following formats:
•
An SDPIF stream conforming to the IEC60958 specification (refer to Figure 17). The following configuration is required to output
an SPDIF stream on the HBR output pins:
•
OVR_MUX_HBR
•
OVR_MUX_HBR
•
A binary stream if one of the following configurations is used:
•
OVR_MUX_HBR
(refer to Figure 14).
•
OVR_MUX_HBR
(refer to Figure 15).
•
OVR_MUX_HBR
to Figure 16).
•
No audio flags are output by the part in these configuration.
•
An AES3 stream on each HBR interface output pin (refer to Figure 18 and Figure 19). The following configuration is required to
output AES3 streams:
•
OVR_MUX_HBR
•
I2SOUTMODE[1:0]
It is important to note that:
•
Each of the four HBR outputs carry one of four consecutive blocks of the HBR stream.
•
The four streams on the four HBR pin are output at one quarter of the audio sample rate, f
Table 13. HBR Interface Description
HBR Interface IO
I2S0
I2S1
I2S2
I2S3
SCLK
LRCLK
MCLKOUT
Note that the audio output mapping controls I2S_SPDIF_MAP_ROT[1:0] also apply to the HBR output signals.
MUX_DSD_OUT
is set to 0 or
is set to 1 and MUX_HBR_OUT
is set to 1, MUX_HBR_OUT
is set to 1, MUX_HBR_OUT
is set to 1, MUX_HBR_OUT
is set to 1.
is set to 0b11.
Function
First block of HBR stream.
Second block of HBR stream
Third block of HBR stream
Fourth block of HBR stream
Bit clock
Data output clock for left and right channel
Audio master clock output
2 S interface is selected according to the type of packet received. DSD/DST
S interface is enabled when part receives audio sample packets
2
selects the output interface.
Description
Automatic DSD/DST output control
Override DSD/DST output control
Description
Override by outputting I
Override by outputting DSD/DST data
is set to 1.
is set to 0, and I2SOUTMODE[1:0]
is set to 0, and I2SOUTMODE[1:0]
is set to 0, and I2SOUTMODE[1:0]
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Hardware User Guide
S data
2
is set to 0x0 for an I 2 S mode binary stream
is set to 0x1 for a right justified stream
is set to 0x2 for a left justified stream (refer
.
S