Analog Devices ADV7610 Hardware User's Manual page 165

Hardware User Guide
VS_INFO_ST, IO, Address 0x61[4] (Read Only)
Latched status of vendor specific InfoFrame detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
VS_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
VS_INFO_ST
0 (default)
1
MS_INFO_ST, IO, Address 0x61[3] (Read Only)
Latched status of MPEG source InfoFrame detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
MS_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
MS_INFO_ST
0 (default)
1
SPD_INFO_ST, IO, Address 0x61[2] (Read Only)
Latched status of SPD InfoFrame detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
SPD_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
SPD_INFO_ST
0 (default)
1
AUDIO_INFO_ST, IO, Address 0x61[1] (Read Only)
Latched status of audio InfoFrame detected interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
AUDIO_INFO_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
AUDIO_INFO_ST
0 (default)
1
AVI_INFO_ST, IO, Address 0x61[0] (Read Only)
Detailed description is available in the Interrupt Architecture Overview section.
HDMI Lvl INT Status 2 register consists of fields: CS_DATA_VALID_ST, INTERNAL_MUTE_ST, AV_MUTE_ST, AUDIO_CH_MD_ST,
HDMI_MODE_ST, GEN_CTL_PCKT_ST, AUDIO_C_PCKT_ST, and GAMUT_MDATA_ST.
CS_DATA_VALID_ST, IO, Address 0x66[7] (Read Only)
Latched status of channel status data valid interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
ICS_DATA_VALID_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
CS_DATA_VALID_ST
0 (default)
1
INTERNAL_MUTE_ST, IO, Address 0x66[6] (Read Only)
Latched status of internal mute interrupt signal. Once set, this bit will remain high until the interrupt is cleared via
INTERNAL_MUTE_CLR. This bit is only valid if enabled via the corresponding INT1 or INT2 interrupt mask bit.
Function
INTERNAL_MUTE_ST
0 (default)
1
Description
No interrupt generated from this register.
VS_INFO_RAW has changed. Interrupt has been generated.
Description
No interrupt generated from this register.
MS_INFO_RAW has changed. Interrupt has been generated.
Description
No interrupt generated from this register.
SPD_INFO_RAW has changed. Interrupt has been generated.
Description
No interrupt generated from this register.
AUDIO_INFO_RAW has changed. Interrupt has been generated.
Description
CS_DATA_VALID_RAW has not changed. An interrupt has not been generated.
CS_DATA_VALID_RAW has changed. An interrupt has been generated.
Description
INTERNAL_MUTE_RAW has not changed. An interrupt has not been generated.
INTERNAL_MUTE_RAW has changed. An interrupt has been generated.
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