Table of Contents
Advertisement
E.1
Early POST Memory Initialization MRC Diagnostic Codes
Memory initialization at the beginning of POST includes multiple functions: discovery, channel training,
validation that the DIMM population is acceptable and functional, initialization of the IMC and other
hardware settings, and initialization of applicable RAS configurations.
The MRC progress codes are displayed to the diagnostic LEDs that show the execution point in the MRC
operational path at each step.
MRC
Upper Nibble
Progress
8h
4h
Code (Hex)
70
0
1
71
0
1
72
0
1
73
0
1
7E
0
1
B0
1
0
B1
1
0
B2
1
0
B3
1
0
B4
1
0
B5
1
0
B6
1
0
B7
1
0
0
0
0
3
0
0
4
0
0
11
0
0
77
0
1
B8
1
0
B9
1
0
BA
1
0
BB
1
0
BC
1
0
BE
1
0
BF
1
0
If a major memory initialization error occurs, preventing the system from booting with data integrity, the MRC
displays a fatal error code on the diagnostic LEDs, and a system halt command is executed. Fatal MRC error
halts do not change the state of the system status LED and they do not get logged as SEL events.
lists all MRC fatal errors that are displayed to the diagnostic LEDs.
Note: Fatal MRC errors display codes that may be the same as BIOS POST progress codes displayed later in
the POST process.
Intel® Server D50DNP Family Integration and Service Guide
Table 18. Memory Reference Code (MRC) Progress Codes
Lower Nibble
2h
1h
8h
4h
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
1
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
2h
1h
0
0
HBM Training
0
1
HBM internal use.
1
0
HBM internal use.
1
1
NVRAM sync.
1
0
MRCinternal sync.
0
0
Detect DIMM population
0
1
Initialize clock
1
0
Gather remaining SPD data
1
1
Gets memory ready to be written and read.
0
0
Evaluate RAS modes and save rank information.
0
1
MRCinternal dispatch.
1
0
DDRIO initialize.
1
1
Train DDR5 channels
0
0
Train DDR5 channels: Receive enable training
1
1
Train DDR5 channels: Read DQ/DQS training
0
0
Train DDR5 channels: Write DQ/DQS training
0
1
Train DDR5 channels: End of channel training.
1
1
Train DDR5 channels: Write leveling training.
0
0
Initialize CLTT/OLTT
0
1
Hardware memory test and initialization
1
0
Execute software memory initialization
1
1
Program memory map and interleaving
0
0
Program RAS configuration
1
0
Execute BSSA RMT
1
1
MRC is done
Description
Table 19
203
Advertisement
Table of Contents
