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Intel® Server System M50CYP2UR Family System Integration and Service Guide
LEDs
Status
Binary
Read
Value
Hexadecimal
Result
Upper nibble bits = 1010b = Ah; Lower nibble bits = 1100b = Ch; the two Hex Nibble values are combined to
create a single ACh POST Progress Code.
E.1
Early POST Memory Initialization MRC Diagnostic Codes
Memory initialization at the beginning of POST includes multiple functions: discovery, channel training,
validation that the DIMM population is acceptable and functional, initialization of the IMC and other
hardware settings, and initialization of applicable RAS configurations.
The MRC progress codes are displayed to the diagnostic LEDs that show the execution point in the MRC
operational path at each step.
Upper Nibble
Post Code
(Hex)
8h
4h
B0
1
0
B1
1
0
B2
1
0
B3
1
0
B4
1
0
B5
1
0
B6
1
0
B7
1
0
1
0
0
2
0
0
3
0
0
4
0
0
5
0
0
B8
1
0
B9
1
0
BA
1
0
132
Table 8. POST Progress Code LED Example
Upper Nibble AMBER LEDs
MSB
LED #7
LED #6
LED #5
8h
4h
ON
OFF
1
0
Ah
Table 9. MRC Progress Codes
Lower Nibble
2h
1h
8h
4h
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
1
1
0
1
1
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
1
1
0
1
1
1
0
1
1
1
0
LED #4
LED #3
2h
1h
ON
OFF
1
0
ACh
2h
1h
Detect DIMM population
0
0
Set DDR4 frequency
0
1
Gather remaining SPD data
1
0
Program registers on the memory controller level
1
1
Evaluate RAS modes and save rank information
0
0
Program registers on the channel level
0
1
Perform the JEDEC defined initialization sequence
1
0
Train DDR4 ranks
1
1
Train DDR4 ranks
0
1
Train DDR4 ranks – Read DQ/DQS training
1
0
Train DDR4 ranks – Receive enable training
1
1
Train DDR4 ranks – Write DQ/DQS training
0
0
Train DDR4 ranks – DDR channel training done
0
1
Initialize CLTT/OLTT
0
0
Hardware memory test and init
0
1
Execute software memory init
1
0
Lower Nibble GREEN LEDs
LED #2
LED #1
8h
4h
2h
ON
ON
OFF
1
1
Ch
Description
LSB
LED #0
1h
OFF
0
0
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