Configuring The Emulation Probe For Maximum Performance (Bdm) - Agilent Technologies E5900B User Manual

Configuring the Emulation Probe for Maximum Performance (BDM)

Configuring the Emulation Probe for Maximum
Performance (BDM)
The performance of the emulation probe depends on the speed at which it
communicates with the target system. Better performance is obtained with
faster communication speeds.
Setting DSCK speed
On BDM debug ports the communication speed is controlled by the clock
signal DSCK. This signal is generated by the emulation probe. You can set the
speed of DSCK using the Emulation Control Interface in a 16700-series logic
analysis system or by using the cf procck command through a telnet or
debugger connection to the emulation probe.
To change DSCK speed, send a cf procck=x (where x is the
Microprocessor System Clock Speed defined in the table below) command to
the probe. The DSCK speed will be set between 1/3 and 1/4 the
Microprocessor System Clock Speed. To restore the factory default, send an
init -c command. For more information about cf procck, send a help cf
procck command to the probe. Also note that some debuggers allow the
BDM communication speed to be set from within their GUI or from a
command file.
Microprocessor
cf procck=
System Clock Speed
80 80 MHz or greater
66 66 MHz or greater
50 50 MHz or greater
33 33 MHz or greater
25 25 MHz or greater
20 20 MHz or greater
16 16 MHz or greater
8 8 MHz or greater
4 4 MHz or greater
1 1 MHz or greater
512 512 KHz or greater
32 32 KHz or greater
E5900B / E5901B User's Guide Supplement
Configuring the Emulator
Approximate BDM DSCK
Speed
26 MHz
22 MHz
16 MHz
11 MHz
8 MHz
6 MHz
5 MHz
2 MHz
1 MHz (Default)
256 KHz
128 KHz
8 KHz
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